Method to induce strain in 3-D microfabricated structures

Patent metadata

Field	Value
Publication number	US-9245953-B2
Application number	US-201514597457-A
Country	US
Kind code	B2
Filing date	Jan 15, 2015
Priority date	Jul 29, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

First claim

What is claimed is:

1. A method for making a strained three-dimensional feature patterned on a substrate, the method comprising:
forming a first semiconductor layer in a strained state at a surface of the substrate;
forming a second semiconductor layer adjacent the first semiconductor layer;
patterning the three-dimensional feature in at least the second semiconductor layer; and
cutting the first semiconductor layer in the vicinity of the patterned three-dimensional feature to relieve strain in the first semiconductor layer and induce strain in the patterned three-dimensional feature.

2. The method of claim 1 , wherein the thickness of the first semiconductor layer is between approximately 10 nm and approximately 60 nm.

3. The method of claim 2 , wherein the thickness of the second semiconductor layer is between approximately 10 nm and approximately 60 nm.

4. The method of claim 1 , wherein the first semiconductor layer comprises SiGe or SiC.

5. The method of claim 4 , further comprising forming the first semiconductor layer with a gradient in Ge or C content in a direction perpendicular to the surface of the substrate.

6. The method of claim 4 , wherein the second semiconductor layer comprises Si.

7. The method of claim 1 , wherein the three-dimensional feature comprises a fin for a finFET device.

8. The method of claim 7 , wherein the cutting comprises etching a pattern for the fin through the first semiconductor layer.

9. The method of claim 8 , wherein 2.55<R sc <3.12 and R sc is defined as:
R sc =L /( T si +T f )

where L represents the length of the fin, T si represents the thickness of the first semiconductor layer, and T f represents the thickness of the second semiconductor layer.

10. The method of claim 9 , wherein T si is a value between approximately 10 nm and approximately 60 nm.

11. The method of claim 9 , wherein the first semiconductor layer comprises SiGe or SiC and the second semiconductor layer comprises Si.

12. The method of claim 9 , further comprising forming a gate structure for a finFET at a center of the fin in the second semiconductor layer.

13. The method of claim 9 , wherein forming the first semiconductor layer comprises epitaxially growing the first semiconductor layer.

14. The method of claim 9 , wherein forming the second semiconductor layer comprises epitaxially growing the second semiconductor layer.

15. The method of claim 9 , wherein patterning the three-dimensional feature and cutting the first semiconductor layer comprise at least one etching process.

16. The method of claim 9 , wherein the fin has a width between approximately 5 nm and approximately 30 nm.

17. A method for making a finFET comprising:
forming a first semiconductor layer in a strained state at a surface of a substrate;
forming a second semiconductor layer adjacent the first semiconductor layer;
forming a fin in at least the second semiconductor layer using a sidewall image transfer process; and
cutting the first semiconductor layer in the vicinity of the fin to relieve strain in the first semiconductor layer to form a strained fin for the finFET.

18. The method of claim 17 , wherein the thickness of the first semiconductor layer is between approximately 10 nm and approximately 60 nm.

19. The method of claim 18 , wherein the thickness of the second semiconductor layer is between approximately 10 nm and approximately 60 nm.

20. The method of claim 17 , wherein the cutting comprises etching a pattern for the fin through the first semiconductor layer.

21. The method of claim 17 , wherein 2.55<R sc <3.12 and R sc is defined as:
R sc =L /( T si +T f )

where L represents the length of the fin, T si represents the thickness of the first semiconductor layer, and T f represents the thickness of the second semiconductor layer.

22. The method of claim 21 , wherein T si is a value between approximately 10 nm and approximately 60 nm.

23. The method of claim 17 , further comprising forming a gate structure for a finFET at a center of the fin in the second semiconductor layer.

24. The method of claim 17 , wherein the fin has a width between approximately 5 nm and approximately 30 nm.

25. A method for making a finFET comprising:
forming a first semiconductor layer in a strained state at a surface of a substrate, the first semiconductor layer comprising SiGe;
forming a second semiconductor layer adjacent the first semiconductor layer, the second semiconductor layer comprising Si;
forming the fin in at least the second semiconductor layer using a sidewall image transfer process; and
cutting the first semiconductor layer in the vicinity of the fin to relieve strain in the first semiconductor layer to form a strained fin for the finFET.

26. The method of claim 25 , wherein the thickness of the first semiconductor layer is between approximately 10 nm and approximately 60 nm.

27. The method of claim 26 , wherein the thickness of the second semiconductor layer is between approximately 10 nm and approximately 60 nm.

28. The method of claim 25 , wherein the cutting comprises etching a pattern for the fin through the first semiconductor layer.

29. The method of claim 25 , wherein 2.55<R sc <3.12 and R sc is defined as:
R sc =L /( T si +T f )

where L represents the length of the fin, T si represents the thickness of the first semiconductor layer, and T f represents the thickness of the second semiconductor layer.

30. The method of claim 29 , wherein T si is a value between approximately 10 nm and approximately 60 nm.

31. The method of claim 25 , further comprising forming a gate structure for a finFET at a center of the fin in the second semiconductor layer.

32. The method of claim 25 , wherein the fin has a width between approximately 5 nm and approximately 30 nm.

Assignees

• St Microelectronics Inc

Inventors

• Loubet Nicolas
• Morin Pierre

Classifications

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/8164

  comprising only semiconductor materials  (potential variation in long-range structurally-disordered materials H10D62/8163) · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title