Method for forming wiring

Patent metadata

Field	Value
Publication number	US-9245789-B2
Application number	US-201314433061-A
Country	US
Kind code	B2
Filing date	Aug 20, 2013
Priority date	Oct 9, 2012
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

The present invention addresses the problem of inhibiting the evolution of a poisoning gas to eliminate wiring-pattern resolution failures and thereby forming a desired wiring layer structure to provide functional elements having an improved property yield. This method for forming multi-layered copper interconnect on a semiconductor substrate comprises: forming a multilayer resist structure to form a given resist pattern on a substrate including an interlayer dielectric film that has via holes which have been formed in part thereof and filled with an SOC layer, the multilayer resist structure comprising an SOC layer, an SOG layer, an SiO 2 layer, and a chemical amplification type resist superposed in this order from the substrate side; conducting etching using the resist pattern as a mask to form a pattern for a wiring layer and via plugs; and forming the wiring layer and the via plugs in the pattern.

First claim

The invention claimed is:

1. A wiring forming method comprising:
forming a multilayer resist structure to form a given resist pattern on a substrate including an interlayer insulating film that has a via hole which have been formed in part thereof and filled with an SOC layer, the multilayer resist structure comprising, at least, an SOC layer, an SOG layer, an SiO 2 layer, and a chemically amplification type resist superposed in this order from the substrate side;
conducting etching using the resist pattern as a mask to form a pattern for a wiring layer and via plugs; and
forming the wiring layer and the via plugs in the pattern.

2. The wiring forming method according to claim 1 , wherein
an SiCN film or an SiN film is exposed at a bottom of the via hole, and a lower layer of the film is made of at least one of WN, TaN and TiN.

3. The wiring forming method according to claim 1 , wherein
the SiO 2 layer is a high density SiO 2 layer whose density is 2.1 g/cm 3 or higher.

4. The wiring forming method according to claim 3 , wherein
the high density SiO 2 layer is formed by use of the high density plasma whose electron density is 10 10 electrons/cm 3 or higher.

5. The wiring forming method according to claim 3 , wherein
the high density SiO 2 layer is formed under the condition that a substrate temperature is 250° C. or lower to 150° C. or higher.

6. The wiring forming method according to claim 1 , wherein
after raw material of organic silica is applied on the substrate which is rotated, the SOG layer is formed by carrying out thermal treatment.

7. The wiring forming method according to claim 1 , wherein
a total of thicknesses of the SOG layer and the SiO 2 layer is 100 nm or less to 50 nm or more.

8. The wiring forming method according to claim 7 , wherein
a thickness of the SOG layer is in an range of 15 nm to 60 nm, and a thickness of the SiO 2 layer is in an range of 30 nm to 80 nm.

9. The wiring forming method according to claim 4 , wherein
the high density plasma (HDP) includes, at least, raw material of silane and oxidizing gas.

10. The wiring forming method according to claim 9 , wherein
the high density plasma (HDP) includes, at least, SiH 4 , N 2 O and Ar.

Assignees

• Nec Corp

Inventors

• Okamoto Koichiro
• Tada Munehiro
• Hada Hiromitsu
• Sakamoto Toshitsugu

Classifications

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10P50/287

  by chemical means · CPC title

• H10P50/285

  of materials not containing Si, e.g. PZT or Al2O3 · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10P50/267

  using plasmas · CPC title