Method for manufacturing a dual work function semiconductor device

Patent metadata

Field	Value
Publication number	US-9245759-B2
Application number	US-201314047849-A
Country	US
Kind code	B2
Filing date	Oct 7, 2013
Priority date	Oct 8, 2012
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element. The method additionally includes annealing to diffuse the first work function-shifting element and the second work function-shifting element into the dielectric layer, and subsequently removing the first metal layer/stack and the second metal layer/stack. The method further includes forming a third metal layer/stack in the first and second predetermined areas.

First claim

What is claimed is:

1. A method of manufacturing a dual work function semiconductor device, the method comprising:
providing a substrate comprising a first predetermined area for forming a transistor of a first conduction type and a second predetermined area for forming a transistor of a second conduction type, the first conduction type being different from the second conduction type;
forming a dielectric layer on the substrate, the dielectric layer extending to cover at least a part of the first area and extending to cover at least a part of the second area;
forming a first metal layer/stack on the dielectric layer in the first predetermined area, wherein the first metal layer/stack comprises a first work function-shifting element,
wherein the first metal layer/stack is one of TiN/Mg/TiN, Mg/TiN, TiN/La/TiN, La, La 2 O 3 or a layer comprising a matrix material containing the first work function-shifting element different from elements of the matrix material;
forming a second metal layer/stack directly on the first metal layer/stack in the first predetermined area and on the dielectric layer in the second predetermined area, wherein the second metal layer/stack comprises a second work function-shifting element;
annealing to diffuse the first work function-shifting element and the second work function-shifting element into the dielectric layer;
removing the first metal layer/stack and the second metal layer/stack; and
forming a third metal layer/stack in the first predetermined area and the second predetermined area.

2. The method of claim 1 , wherein the first metal layer/stack is formed of a matrix material that is formed of a metal, a metal compound or a dielectric that contains the first work function-shifting element.

3. The method of claim 2 , wherein the work function-shifting element is a rare earth metal selected from the group consisting of La, Gd, Tb, Er, Yb, Dy, Lu, Y, and Sc.

4. The method of claim 2 , wherein the matrix material is an oxide or a nitride.

5. The method of claim 2 , wherein the work function-shifting element is an alkaline earth metal.

6. The method of claim 5 , wherein the work function-shifting element is Mg or Sr.

7. A method of manufacturing a dual work function semiconductor device, the method comprising:
providing a substrate comprising a first predetermined area for forming a transistor of a first conduction type and a second predetermined area for forming a transistor of a second conduction type, the first conduction type being different from the second conduction type;
forming a dielectric layer on the substrate, the dielectric layer extending to cover at least a part of the first area and extending to cover at least a part of the second area;
providing an etch stop layer on the dielectric layer,
wherein the etch stop layer is substantially etch-resistant to an etchant adapted for etching the first metal layer/stack and/or the second metal layer/stack, and
wherein the etch stop layer is adapted for allowing diffusion of the first work function-shifting element and the second work function-shifting element there through;
forming a first metal layer/stack on the etch stop layer in the first predetermined area, wherein the first metal layer/stack comprises a first work function-shifting element;
forming a second metal layer/stack on the first metal layer/stack in the first predetermined area and on the etch stop layer in the second predetermined area, wherein the second metal layer/stack comprises a second work function-shifting element;
annealing to diffuse the first work function-shifting element and the second work function-shifting element into the dielectric layer;
removing the first metal layer/stack and the second metal layer/stack; and
forming a third metal layer/stack in the first predetermined area and the second predetermined area.

8. The method of claim 7 , comprising an independent anneal process for diffusion of the first work function-shifting elements into the dielectric layer, before depositing the second metal layer/stack comprising the second work function-shifting element.

9. The method of claim 7 , wherein annealing does not provide diffusion of the second work function-shifting element into the dielectric layer in the first predetermined area.

10. The method of claim 7 , wherein the etch stop layer comprises at least one of TaN, Ta, TaO Ta 2 O 3 and TiN.

11. The method of claim 10 , wherein the etch stop layer comprises a bi-layer including a TaN layer and one of a TaO layer and a Ta 2 O 3 layer.

12. The method of claim 10 , wherein the etch stop layer comprises a bi-layer including a TiN layer and one of a TaO layer and Ta 2 O 3 layer.

13. The method of claim 7 , wherein the first metal layer/stack, or the second metal layer/stack comprises one of TiN/Mg/TiN, Mg/TiN, La, La 2 O 3 , and TiN/La/TiN.

14. The method of claim 7 , wherein at least one of the first metal layer/stack and the second metal layer/stack comprises aluminum.

15. The method of claim 14 , wherein at least one of the first metal layer/stack and the second metal layer/stack comprises aluminum oxide covered with a layer of TiN, or covered with a trilayer comprising TiN/Al/TiN.

16. The method of claim 14 , wherein at least one of the first metal layer/stack and the second metal layer/stack comprises aluminum oxide covered with a trilayer comprising TiN/Al/TiN.

17. The method of claim 7 , wherein the etch stop layer has a thickness between about 0.5 nm and 20 nm.

18. The method of claim 7 ,
wherein providing the substrate comprises providing an isolation area electrically isolating the first predetermined area from the second predetermined area, and
wherein the method further comprises removing a portion of the dielectric layer, the etch stop layer, and the third metal layer/stack at a location above the isolation region.

19. The method of claim 7 , wherein the dielectric layer comprises a high-k dielectric.

20. The method of claim 19 , wherein the high-k dielectric comprises one of HfO 2 , HfSiO, HfSiN, ZrO 2 , and a doped hafnium oxide.

Assignees

• Imec

Inventors

• Schram Tom
• Caillat Christian
• Spessot Alessio
• Fazan Pierre
• Ragnarsson Lars-Ake
• Ritzenthaler Romain

Classifications

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D64/013 Primary

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/0181

  Manufacturing their gate insulating layers · CPC title