Global stores and atomic operations

Patent metadata

Field	Value
Publication number	US-9245371-B2
Application number	US-84976610-A
Country	US
Kind code	B2
Filing date	Aug 3, 2010
Priority date	Sep 11, 2009
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

One embodiment of the present invention sets forth a method for storing processed data within buffer objects stored in buffer object memory from within shader engines executing on a GPU. The method comprises the steps of receiving a stream of one or more shading program commands via a graphics driver, executing, within a shader engine, at least one of the one or more shading program commands to generate processed data, determining from the stream of one or more shading program commands an address associated with a first data object stored within the buffer memory, and storing, from within the shader engine, the processed data in the first data object stored within the buffer memory.

First claim

We claim:

1. A computer-implemented method for accessing data objects stored within a buffer memory, the method comprising:
receiving a stream of one or more shading program commands via a graphics driver that executes within a central processing unit;
executing, within a shader engine, at least one of the one or more shading program commands to generate processed data;
determining from the stream of one or more shading program commands an address generated by the graphics driver and included in the at least one of the one or more shading program commands, wherein the address is associated with a first data object stored within the buffer memory; and
storing, from within the shader engine, the processed data in the first data object stored within the buffer memory,
wherein the first data object has been bound to a context of an application program by the graphics driver to provide the shader engine with access to the first data object, and the application program is associated with the stream of one or more shading program commands.

2. The method of claim 1 , wherein the address associated with the first data object is specified as a high-level language pointer.

3. The method of claim 2 , wherein the step of storing the processed data comprises dereferencing the high-level language pointer to access the first data object.

4. The method of claim 1 , wherein the stream of one or more commands includes a first command for processing vertex attributes to generate the processed data.

5. The method of claim 1 , wherein the stream of one or more commands includes a first command for processing vertex information stored in a second data object within the buffer memory to generate the processed data.

6. The method of claim 1 , wherein the stream of one or more commands includes a first command for processing primitive information stored in a second data object within the buffer memory to generate the processed data.

7. The method of claim 1 , wherein a first command comprises an atomic memory transaction command that specifies an operation to be performed on data currently stored in the first data object to generate the processed data.

8. The method of claim 7 , wherein data previously stored in the first data object is read, a computation involving a value and an operation specified in the atomic memory transaction is performed, and the result is stored in the first data object.

9. The method of claim 8 , wherein no other memory transactions involving the data stored in the first data object are permitted for the duration of the atomic memory transaction.

10. The method of claim 8 , where the value previously stored in the first data object is returned to the shading engine for further processing.

11. The method of claim 1 , wherein the address associated with the first data object remains unchanged for the lifetime of the first data object.

12. The method of claim 1 , wherein the address associated with the first data object comprises a virtual memory address, and further comprising the step of translating the virtual memory address into a physical memory address.

13. The method of claim 1 , wherein the application program transmits a make-resident command to the graphics driver to make the first data object resident in the buffer memory.

14. The method of claim 13 , wherein the application program transmits a make-nonresident command to the graphics driver to indicate that the first data object need not remain resident in buffer memory.

15. A parallel processing subsystem, comprising:
a processor that is configured to:
receive a stream of one or more shading program commands via a graphics driver that executes within a central processing unit;
execute at least one of the one or more shading program commands to generate processed data;
determine from the stream of one or more shading program commands an address generated by the graphics driver and included in the at least one of the one or more shading program commands, wherein the address is associated with a first data object stored within the buffer memory; and
store, from within the shader engine, the processed data in the first data object stored within the buffer memory,
wherein the first data object becomes bound to a context of an application program by the graphics driver to provide the shader engine with access to the first data object, and the application program is associated with the stream of one or more shading program commands.

16. The parallel processing subsystem of claim 15 , wherein the address associated with the first data object is specified as a high-level language pointer.

17. The parallel processing subsystem of claim 16 wherein the step of storing the processed data comprises dereferencing the high-level language pointer to access the first data object.

18. The parallel processing subsystem of claim 15 , wherein the stream of one or more commands includes a first command for processing vertex attributes to generate the processed data.

19. The parallel processing subsystem of claim 15 , wherein the stream of one or more commands includes a first command for processing vertex information stored in a second data object within the buffer memory to generate the processed data.

20. The parallel processing subsystem of claim 15 , wherein the stream of one or more commands includes a first command for processing primitive information stored in a second data object within the buffer memory to generate the processed data.

21. The parallel processing subsystem of claim 15 , wherein a first command comprises an atomic command that specifies an operation to be performed on data currently stored in the first data object to generate the processed data.

22. The parallel processing subsystem of claim 15 , wherein the one or more shading program commands are specified as text-based assembly language commands.

23. A computer system, comprising:
a central processing unit (CPU),
a graphics processing unit (GPU), and
a shader engine executing on the GPU and configured to:
receive a stream of one or more shading program commands via a graphics driver that executes within the CPU,
execute at least one of the one or more shading program commands to generate processed data,
determine from the stream of one or more shading program commands an address generated by the graphics driver and included in the at least one of the one or more shading program commands, wherein the address is associated with a first data object stored within a buffer memory, and
store the processed data in the first data object stored within the buffer memory,
wherein the first data object becomes bound to a context of an application program by the graphics driver to provide the shader engine with access to the first data object, and the application program is associated with the stream of one or more shading program commands.

Assignees

• Bolz Jeffrey A
• Brown Patrick R
• Nvidia Corp

Inventors

• Bolz Jeffrey A
• Brown Patrick R

Classifications

• G09G5/363

  Graphics controllers · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06F13/1605

  based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36) · CPC title

• G06T15/80

  Shading · CPC title