Tunable multi-tiered STT-MRAM cache for multi-core processors

Patent metadata

Field	Value
Publication number	US-9244853-B2
Application number	US-201213571426-A
Country	US
Kind code	B2
Filing date	Aug 10, 2012
Priority date	Aug 10, 2012
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A multi-core processor is presented. The multi-core processor includes a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache associated with a first core of the multi-core processor and tuned according to first attributes and a second STT-MRAM cache associated with a second core of the multi-core processor and tuned according to second attributes.

First claim

What is claimed is:

1. A multi-core processor, comprising:
a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache comprising a first type of metal tunnel junctions (MTJs) having a first size and associated with a first core of the multi-core processor and tuned according to first attributes; and
a second STT-MRAM cache comprising a second type of MTJs having a second size that is greater than the first type of MTJs and associated with a second core of the multi-core processor and tuned according to second attributes, wherein the first attributes are different from the second attributes, at least one other core is associated with the first STT-MRAM cache or the second STT-MRAM cache, and each of the first STT-MRAM cache and the second STT-MRAM cache is configurable as a lower level cache, a mid-level cache or a high level cache.

2. The multi-core processor of claim 1 , in which the first STT-MRAM cache and the second STT-MRAM cache are a lower level cache.

3. The multi-core processor of claim 1 , in which the first STT-MRAM cache and the second STT-MRAM cache are a mid-level cache.

4. The multi-core processor of claim 1 , in which the first STT-MRAM cache and the second STT-MRAM cache are embedded or monolithically integrated with each core.

5. The multi-core processor of claim 1 , in which the first attributes and second attributes comprise at least latency, cache hit/miss rate, energy, energy-delay product, data utilization, area size, capacity size, and/or data reliability.

6. The multi-core processor of claim 1 , in which each core is associated with one type of STT-MRAM cache.

7. The multi-core processor of claim 1 , further comprising a third STT-MRAM cache associated with a third core of the multi-core processor and tuned according to third attributes.

8. The multi-core processor of claim 1 , in which the first STT-MRAM cache and the second STT-MRAM cache are fabricated utilizing a homogeneous lower level integration process.

9. The multi-core processor of claim 1 , wherein the multi-core processor is integrated in a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

10. A multi-core processor, comprising:
a first storage means comprising a first type of spin transfer torque (STT) magnetoresistive means having a first size associated with a first core of the multi-core processor and tuned according to first attributes; and
a second storage means comprising a second type of STT magnetoresistive means having a second size that is greater than the first type of STT magnetoresistive means associated with a second core of the multi-core processor and tuned according to second attributes, wherein the first attributes are different from the second attributes, at least one other core is associated with the first storage means or the second storage means, and each of the first storage means and the second storage means is configurable as a lower level cache, a mid-level cache or a high level cache.

11. The multi-core processor of claim 10 , integrated in a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

12. A method for associating caches in a multi-core processor, comprising:
a step of associating a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache comprising a first type of metal tunnel junctions (MTJs) having a first size with a first core of the multi-core processor and tuned according to first attributes;
a step of associating a second STT-MRAM cache with a second core of the multi-core processor comprising a second type of MTJs having a second size that is greater than the first type of MTJs and tuned according to second attributes, wherein the first attributes are different from the second attributes and each of the first STT-MRAM cache and the second STT-MRAM cache is configurable as a lower level cache, a mid-level cache or a high level cache; and
a step of associating the first STT-MRAM cache or the second STT-MRAM cache with at least one other core.

13. The method of claim 12 , further comprising a step of integrating the multi-core processor in a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

14. A method for associating caches in a multi-core processor, comprising:
associating a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache comprising a first type of metal tunnel junctions (MTJs) having a first size with a first core of the multi-core processor and tuned according to first attributes;
associating a second STT-MRAM cache comprising a second type of MTJs having a second size that is greater than the first type of MTJs with a second core of the multi-core processor and tuned according to second attributes, wherein the first attributes are different from the second attributes, and each of the first STT-MRAM cache and the second STT-MRAM cache is configurable as a lower level cache, a mid-level cache or a high level cache; and
associating the first STT-MRAM cache or the second STT-MRAM cache with at least one other core.

15. The method of claim 14 , in which the first STT-MRAM cache and the second STT-MRAM cache are a lower level cache.

16. The method of claim 14 , in which the associating comprises embedding or monolithically integrating the first STT-MRAM cache and the second STT-MRAM cache with each core.

17. The method of claim 14 , further comprising integrating the multi-core processor in a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

18. A method for fabricating caches for a multi-core processor, the method comprising:
tuning a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache comprising a first type of metal tunnel junctions (MTJs) having a first size according to first attributes;
tuning a second STT-MRAM cache comprising a second type of MTJs having a second size that is greater than the first type of MTJs according to second attributes, wherein the first attributes are different from the second attributes, and each of the first STT-MRAM cache and the second STT-MRAM cache is configurable as a lower level cache, a mid-level cache or a high level cache; and
associating the first STT-MRAM cache or the second STT-MRAM cache with at least one other core.

19. The method of claim 18 , in which the first attributes and second attributes comprise at least latency, cache hit/miss rate, energy, energy-delay product, data utilization, area size, capacity size, and/or data reliability.

20. The method of claim 19 , further comprising utilizing a homogeneous lower level integration process when tuning the first STT-MRAM cache and the second STT-MRAM cache.

21. The method of claim 18 , further comprising integrating the multi-core processor in a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a compute

Assignees

• Kang Seung H
• Zhu Xiaochun
• Wu Xiaoxia
• Qualcomm Inc

Inventors

• Kang Seung H
• Zhu Xiaochun
• Wu Xiaoxia

Classifications

• G06F2212/222

  Non-volatile memory · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0806

  Multiuser, multiprocessor or multiprocessing cache systems · CPC title

• G06F12/0893 Primary

  Caches characterised by their organisation or structure · CPC title

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title