Processing multi-destination instruction in pipeline by splitting for single destination operations stage and merging for opcode execution operations stage
US-9223577-B2 · Dec 29, 2015 · US
Microprocessor that translates conditional load/store instructions into variable number of microinstructions
US9244686B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9244686-B2 |
| Application number | US-201214007116-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 6, 2012 |
| Priority date | Apr 7, 2011 |
| Publication date | Jan 26, 2016 |
| Grant date | Jan 26, 2016 |
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Abstract
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An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.
First claim
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We claim: 1. A microprocessor, comprising: condition flags; an instruction translator, that receives a conditional load/store instruction that specifies a condition, a destination/data register, a base register, an offset source, and a memory addressing mode, wherein the instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load instruction) or store data to the memory location from the data register (conditional…
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- G06F9/3017Primary
Physics · mapped topic
- G06F9/30076Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9244686B2 cover?
- An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) on…
- Who is the assignee on this patent?
- Henry G Glenn, Parks Terry, Hooker Rodney E, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G06F9/3017. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 26 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).