Polar modulator

Patent metadata

Field	Value
Publication number	US-9240919-B2
Application number	US-201314401183-A
Country	US
Kind code	B2
Filing date	Jun 18, 2013
Priority date	Jun 20, 2012
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A polar modulator ( 200 ) comprises a modulation generator ( 10 ) arranged to generate phase modulation data and amplitude modulation data; and a phase modulation stage ( 20 ) arranged to generate a phase modulated, PM, carrier signal and a PM clock signal, wherein the PM carrier signal has a PM carrier signal frequency and the PM clock signal has a PM clock signal frequency, and the PM carrier signal frequency is higher than the PM clock signal frequency, the PM carrier signal and the PM clock signal are phase modulated by the phase modulation data, and the phase modulation stage ( 20 ) comprises an adjustable delay stage ( 50 ) arranged to adjust a relative delay between the PM carrier signal and the PM clock signal to a target value. The polar modulator ( 200 ) further comprises a re-timing circuit ( 40 ) arranged to generate an amplitude modulation, AM, clock signal by re-timing the PM clock signal with the PM carrier signal; an amplitude modulation stage ( 30 ) arranged to employ the AM clock signal to clock the amplitude modulation data into the amplitude modulation stage ( 30 ) and arranged to amplitude modulate the PM carrier signal with the amplitude modulation data; an error detection stage ( 60 ) arranged to generate an indication of a magnitude of a first deviation of the AM clock signal from a target condition; and a control stage ( 70 ) arranged to select the target value of the relative delay by determining, by controlling the adjustment of the relative delay by the adjustable delay stage ( 50 ), a first value of the relative delay that maximizes the magnitude of the first deviation, and applying an offset to the first value of the relative delay.

First claim

The invention claimed is:

1. A polar modulator comprising:
a modulation generator arranged to generate phase modulation data and amplitude modulation data;
a phase modulation stage arranged to generate a phase modulated, PM, carrier signal and a PM clock signal, wherein:
the PM carrier signal has a PM carrier signal frequency and the PM clock signal has a PM clock signal frequency, and the PM carrier signal frequency is higher than the PM clock signal frequency,
the PM carrier signal and the PM clock signal are phase modulated by the phase modulation data, and
the phase modulation stage comprises an adjustable delay stage arranged to adjust a relative delay between the PM carrier signal and the PM clock signal to a target value;

a re-timing circuit arranged to generate an amplitude modulation, AM, clock signal by re-timing the PM clock signal with the PM carrier signal;
an amplitude modulation stage arranged to employ the AM clock signal to clock the amplitude modulation data into the amplitude modulation stage and arranged to amplitude modulate the PM carrier signal with the amplitude modulation data;
an error detection stage arranged to generate an indication of a magnitude of a first deviation of the AM clock signal from a target condition; and
a control stage arranged to select the target value of the relative delay by determining, by controlling the adjustment of the relative delay by the adjustable delay stage, a first value of the relative delay that maximizes the magnitude of the first deviation, and applying an offset to the first value of the relative delay.

2. A polar modulator as claimed in claim 1 , wherein:
the error detection stage is arranged to generate an indication of a magnitude of a second deviation of the AM clock signal from the target condition, wherein the first deviation and the second deviation have opposite polarities; and
the control stage is arranged to determine a second value of the relative delay that maximizes the magnitude of the second deviation and arranged to select the offset in the range 40% to 60% of a difference between the first and second values of the relative delay.

3. A polar modulator as claimed in claim 1 , wherein the offset is in the range 40% to 60% of the period of the PM carrier signal.

4. A polar modulator as claimed in claim 1 , wherein the target condition is a duty cycle of fifty percent.

5. A polar modulator as claimed in claim 1 , wherein the error detection stage is arranged to generate the indication of magnitude as an average value of the AM clock signal.

6. A polar modulator as claimed in claim 1 , wherein the AM clock signal has a differential format comprising a first differential component and a second differential component, and wherein the target condition is simultaneous switching of polarity of the first and second differential components.

7. A polar modulator as claimed in claim 6 , wherein the error detection stage is arranged to generate the indication of magnitude as an average value of a logical AND function of the first and second differential components of the AM clock signal.

8. A polar modulator as claimed in claim 1 , wherein the re-timing circuit comprises a latch arranged to re-time the PM clock signal with the PM carrier signal by latching the PM clock signal with an edge of the PM carrier signal.

9. A polar modulator as claimed in claim 1 , wherein the adjustable delay stage is arranged to adjust the relative delay between the PM carrier signal and the PM clock signal by means of a digital sequence generator arranged to adjust at least one of a phase and a duty cycle of the PM carrier signal.

10. A polar modulator as claimed in claim 9 , wherein the digital sequence generator is arranged to generate a plurality of digital sequences each corresponding to a different combination of phase and duty cycle of the PM carrier signal, and wherein the control stage comprises a look-up table mapping each of the digital sequences to a value of the relative delay.

11. A polar modulator as claimed in claim 9 , wherein the adjustable delay stage is arranged to adjust the relative delay between the PM carrier signal and the PM clock signal by varying at least one of a supply voltage and a supply current of the digital sequence generator.

12. A polar modulator as claimed in claim 1 , wherein the PM carrier signal frequency is at least eight times the PM clock signal frequency.

13. A polar modulator as claimed in claim 1 , wherein the modulation generator generates the phase modulation data and the amplitude modulation data at a rate dependent on the PM clock signal frequency.

14. A wireless communication apparatus comprising a polar modulator as claimed in claim 1 .

15. A polar modulator as claimed in claim 1 , wherein the re-timing circuit is arranged to receive the PM carrier signal from the adjustable delay stage and the PM clock signal from the modulation generator and output the AM clock signal generated from the PM carrier and PM clock signals.

16. A polar modulator as claimed in claim 1 , wherein the error detection stage is arranged to receive the AM clock signal from the re-timing circuit and provide the indication of the magnitude of the first deviation of the AM clock signal from the target condition to the control stage.

17. A polar modulator as claimed in claim 1 , wherein the amplitude modulation stage is arranged to receive the AM clock signal from the re-timing circuit, the amplitude modulation data from the modulation generator, and the PM carrier signal from the adjustable delay stage.

18. A method of calibrating a polar modulator, comprising:
generating phase modulation data;
generating a phase modulated, PM, carrier signal and a PM clock signal, wherein
the PM carrier signal has a higher frequency than the PM clock signal,
the PM carrier signal and the PM clock signal are phase modulated by the phase modulation data;

generating an amplitude modulation, AM, clock signal by re-timing the PM clock signal with the PM carrier signal;
generating an indication of a magnitude of a first deviation of the AM clock signal from a target condition;
adjusting a relative delay between the PM carrier signal and the PM clock signal to determine a first value of the relative delay which maximizes the magnitude of the first deviation;
selecting a target value of the relative delay by applying an offset to the first value of the relative delay; and
adjusting the relative delay to the target value.

Assignees

• St Ericsson Sa

Inventors

• Visser Hendrik
• Heijna Roeland

Classifications

• H04B14/008

  Polarisation modulation · CPC title

• H04W52/0209

  in terminal devices · CPC title

• H04L27/36 Primary

  Modulator circuits; Transmitter circuits · CPC title

• H04L27/361 Primary

  Modulation using a single or unspecified number of carriers, e.g. with separate stages of phase and amplitude modulation · CPC title

• H03C5/00 Primary

  Amplitude modulation and angle modulation produced simultaneously or at will by the same modulating signal (H03C7/00 takes precedence) · CPC title