Analog signal compatible CMOS switch as an integrated peripheral to a standard microcontroller

Patent metadata

Field	Value
Publication number	US-9240785-B2
Application number	US-201414536786-A
Country	US
Kind code	B2
Filing date	Nov 10, 2014
Priority date	Jan 18, 2012
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

At least one analog signal compatible complementary metal oxide semiconductor (CMOS) switch circuit is incorporated with digital logic circuits in an integrated circuit. The integrated circuit may further comprise a digital processor and memory, e.g., microcontroller, microprocessor, digital signal processor (DSP), programmable logic array (PLA), application specific integrated circuit (ASIC), etc., for controlling operation of the at least one analog signal compatible CMOS switch for switching analog signals, e.g., audio, video, serial communications, etc. The at least one analog signal compatible CMOS switch may have first and second states, e.g., single throw “on” or “off”, or double throw common to a or b, controlled by a single digital control signal of either a logic “0” or a logic “1”.

First claim

What is claimed is:

1. An microcontroller, comprising:
a plurality of external input/output connection;
a digital processor;
a memory coupled to the digital processor; and
at least one analog signal compatible complementary metal oxide semiconductor (CMOS) switch coupled to and controlled by the digital processor, and configured to switch signals through a first and a second external input/output connection of said plurality of external input/output connections, wherein the at least one analog signal compatible CMOS switch comprises a first switching node coupled with the first external input/output connection of said plurality of external input/output connections and a second switching node coupled with the second external input/output connection of said plurality of external input/output connections, and
wherein the at least one analog signal compatible CMOS switch provides
a low impedance between the first external input/output connection and the second external input/output connection when the digital processor asserts a control signal at a first logic level thereto, and
a high impedance between the first external input/output connection and the second external input/output connection when the digital processor asserts the control signal at a second logic level thereto.

2. The microcontroller according to claim 1 , wherein the first logic level is a logic level high and the second logic level is a logic level low.

3. The microcontroller according to claim 1 , wherein the first logic level is a logic level low and the second logic level is a logic level high.

4. The microcontroller according to claim 1 , wherein the microcontroller comprises a plurality of analog signal compatible CMOS switches.

5. The microcontroller according to claim 1 , wherein the at least one analog signal compatible CMOS switch comprises:
a P-channel metal oxide semiconductor (P-MOS) transistor having a source, gate and drain;
an N-channel metal oxide semiconductor (N-MOS) transistor having a source, gate and drain; and
an inverter;
wherein:
the drain of the P-MOS transistor is coupled to the source of the N-MOS transistor and the first node,
the source of the P-MOS transistor is coupled to the drain of the N-MOS transistor and the second node,
the gate of the P-MOS transistor and an input of the inverter are coupled to a digital control output of the digital processor, and
the gate of the N-MOS transistor is coupled to an output of the inverter.

6. The microcontroller according to claim 1 , further comprising an integrated circuit package enclosing the integrated circuit device.

7. The microcontroller according to claim 1 ,
wherein the at least one analog signal compatible CMOS switch comprises a third switching node coupled with a third external input/output connection of said plurality of external connections, wherein the at least one analog signal compatible single pole double throw CMOS switch provides
the low impedance between the first external input/output connection and the second external input/output connection and a high impedance between the first external input/output connection and the third external input/output connection when the digital processor asserts the control signal at the first logic level thereto, and
the high impedance between the first external input/output connection and the second external input/output connection and a low impedance between the first external input/output connection and the third external input/output connection when the digital processor asserts the control signal at the second logic level thereto.

8. The microcontroller according to claim 7 , wherein the first logic level is a logic level high and the second logic level is a logic level low.

9. The microcontroller according to claim 7 , wherein the first logic level is a logic level low and the second logic level is a logic level high.

10. The microcontroller according to claim 7 , wherein the microcontroller comprises a plurality of analog signal compatible single pole double throw CMOS switches.

11. The microcontroller according to claim 7 , wherein the CMOS switch comprises:
a first P-channel metal oxide semiconductor (P-MOS) transistor having a source, gate and drain;
a second P-channel metal oxide semiconductor (P-MOS) transistor having a source, gate and drain;
a first N-channel metal oxide semiconductor (N-MOS) transistor having a source, gate and drain;
a second N-channel metal oxide semiconductor (N-MOS) transistor having a source, gate and drain;
a first inverter; and
a second inverter;
wherein:
the drain of the first P-MOS transistor is coupled to the source of the first N-MOS transistor and the first node,
the source of the first P-MOS transistor is coupled to the drain of the first N-MOS transistor and the second node,
the gate of the first P-MOS transistor and an input of the first inverter are coupled to a digital control output of the digital processor,
the gate of the first N-MOS transistor is coupled to an output of the first inverter,
the drain of the second P-MOS transistor is coupled to the source of the second N-MOS transistor and the first node,
the source of the second P-MOS transistor is coupled to the drain of the second N-MOS transistor and the third node,
the gate of the second N-MOS transistor and an input of the second inverter are coupled to the digital control output of the digital processor, and
the gate of the second P-MOS transistor is coupled to an output of the second inverter.

12. The microcontroller according to claim 7 , further comprising an integrated circuit package enclosing the integrated circuit device.

13. The microcontroller according to claim 1 ,
wherein the at least one analog signal compatible switch further comprises a third switching node coupled with a third external input/output connection of said plurality of external connections, wherein the at least one analog signal compatible single pole double throw CMOS switch provides
a high impedance between the first external input/output connection and the second external input/output connection and a low impedance between the first external input/output connection and a third external input/output connection when the digital processor asserts control signals at first logic levels thereto,
a high impedance between the first external input/output connection and the second external input/output connection and a high impedance between the first external input/output connection and the third external input/output connection when the digital processor asserts control signals at second logic levels thereto,
a low impedance between the first external input/output connection and the second external input/output connection and a low impedance between the first external input/output connection and the third external input/output connection when the digital processor asserts control signals at third logic levels thereto, and
a low impedance between the first external input/output connection and the second external input/output connection and a high impedance between the first external input/output connection and the third external input/output connection when the digital processor asserts control signals at fourth logic levels thereto.

14. The microcontroller according to claim 13 , wherein the first logic levels are binary 00, the second logic levels are binary 01, the third logic levels are binary 10, and the fourth logic levels are binary 11.

15. The microcontroller according to claim 13 , wherein the microcontroller comprises a plurality of analog signal compatible single pole CMOS switches.

Assignees

• Microchip Tech Inc

Inventors

• Russell James K

Classifications

• H03K19/0013 Primary

  in field effect transistor circuits · CPC title

• H03K19/0941

  of complementary type · CPC title

• H03K19/0005

  Modifications of input or output impedance · CPC title

• H03K17/002

  Switching arrangements with several input- or output terminals (code converters H03M5/00, H03M7/00) · CPC title

• H03K17/6877

  the control circuit comprising active elements different from those used in the output circuit · CPC title