System and method of protecting a low voltage capacitor of an error amplifier operating in a higher voltage domain
US-2024097620-A1 · Mar 21, 2024 · US
US9240760B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9240760-B2 |
| Application number | US-201414540141-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 13, 2014 |
| Priority date | Jul 5, 2013 |
| Publication date | Jan 19, 2016 |
| Grant date | Jan 19, 2016 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A power amplifier module includes a first amplification transistor that amplifies and outputs a radio frequency signal, a second amplification transistor that is connected in parallel to the first amplification transistor and that has a smaller size than the first amplification transistor, a bias circuit that supplies a bias voltage or a bias current to the first and second amplification transistors, a current detector circuit that detects a current flowing in the second amplification transistor, and a bias control circuit that controls the bias voltage or the bias current supplied from the bias circuit to the first and second amplification transistors depending on the detection result of the current detector circuit.
Opening claim text (preview).
What is claimed is: 1. A power amplifier module comprising: a first amplification transistor configured to amplify and output a radio frequency signal; a second amplification transistor connected in parallel to the first amplification transistor and having a smaller size than the first amplification transistor; a bias circuit configured to supply a bias voltage or a bias current to the first and second amplification transistors; a current detector circuit configured to detect a current flowing in the second amplification transistor; a bias control circuit configured to control the bias voltage or the bias current supplied from the bias circuit to the first and second amplification transistors depending on the detection result of the current detector circuit; and a reference voltage generator circuit configured to generate a predetermined reference voltage, wherein the current detector circuit includes a detection resistor connected in series to the second amplification transistor, the detection resistor being configured to generate a detection voltage corresponding to the current flowing in the second amplification transistor, and wherein the bias control circuit includes a comparator circuit configured to compare the detection voltage with the reference voltage, and a first bias-reducing circuit configured to reduce the bias voltage or the bias current when the detection voltage is greater than the predetermined reference voltage on the basis of the comparison result of the comparator circuit. 2. The power amplifier module according to claim 1 , wherein a number of fingers of the second amplification transistor is smaller than a number of fingers of the first amplification transistor. 3. The power amplifier module according to claim 2 , wherein the fingers of the first and second amplification transistors have a same emitter size. 4. The power amplifier module according to claim 1 , wherein the bias circuit includes a bias adjusting circuit configured to supply the bias current corresponding to a ratio of a size of the first and second amplification transistors to a size of the first and second amplification transistors. 5. The power amplifier module according to claim 1 , further comprising: a first capacitor disposed in a supply path of the radio frequency signal to the first amplification transistor; a second capacitor disposed in a supply path of the radio frequency signal to the second amplification transistor and having a capacitance value smaller than that of the first capacitor, the capacitance value of the second capacitor being based on a ratio of a size of the first amplification transistor to a size of the second amplification transistor. 6. The power amplifier module according to claim 1 , further comprising a reference current generator circuit configured to generate a predetermined reference current, wherein the reference voltage generator circuit includes a reference resistor formed on a same chip as the detection resistor and configured to generate the reference voltage on the basis of the reference current. 7. The power amplifier module according to claim 1 , wherein the bias circuit includes a non-inverting amplifier circuit configured to generate a bias voltage corresponding to an input voltage, and wherein the first bias-reducing circuit is configured to control the non-inverting amplifier circuit so as to reduce the bias voltage when the detection voltage is greater than the predetermined reference voltage. 8. The power amplifier module according to claim 7 , wherein the non-inverting amplifier circuit includes an operational amplifier having an output terminal configured to output the bias voltage, a non-inverted input terminal supplied with the input voltage, and an inverted input terminal connected to the output terminal via a first resistor and grounded via a second resistor, and wherein the first bias-reducing circuit includes a current circuit configured to cause a current to flow in the inverted input terminal of the non-inverting amplifier circuit when the detection voltage is greater than the predetermined reference voltage. 9. The power amplifier module according to claim 7 , wherein the non-inverting amplifier circuit includes an operational amplifier having an output terminal configured to output the bias voltage, an inverted input terminal connected to the output terminal via a first resistor and grounded via a second resistor, and a non-inverted input terminal configured to be supplied with the input voltage via a third resistor, and wherein the first bias-reducing circuit includes a current circuit configured to cause a current to flow from between the third resistor and the non-inverted input terminal of the non-inverting amplifier circuit to the ground when the detection voltage is greater than the predetermined reference voltage. 10. The power amplifier module according to claim 1 , wherein the bias circuit includes a current generator circuit configured to generate a bias current corresponding to the input voltage, and wherein the bias-reducing circuit is configured to control the current generator circuit so as to reduce the bias current when the detection voltage is greater than the predetermined reference voltage. 11. The power amplifier module according to claim 10 , wherein the current generator circuit is configured to be supplied with the input voltage via a fourth resistor, and wherein the bias-reducing circuit includes a current circuit configured to decrease the input voltage supplied to the current generator circuit by causing a current to flow from between the fourth resistor and the current generator circuit to the ground when the detection voltage is greater than the predetermined reference voltage. 12. The power amplifier module according to claim 10 , wherein the bias-reducing circuit includes a current circuit configured to cause a part of the bias current to flow to the ground when the detection voltage is greater than the predetermined reference voltage. 13. The power amplifier module according to claim 1 , wherein the bias control circuit includes a control voltage generator circuit configured to generate a control voltage corresponding to the detection voltage, a clamp circuit configured to clamp the control voltage to be equal to or less than the predetermined reference voltage, a control current generator circuit configured to generate a control current corresponding to the control voltage clamped by the clamp circuit, and a second bias-reducing circuit configured to reduce the bias voltage based on the control current. 14. The power amplifier module according to claim 13 , wherein the bias circuit includes a first constant current circuit configured to output a first constant current, a fifth resistor connected to the first constant current circuit in series, and an amplifier circuit configured to amplify a voltage at one end of the fifth resistor so as to output the amplified voltage, and wherein a second bias-reducing circuit controls an amount of current which is input from the first constant current circuit to the fifth resistor based on the control current. 15. The power amplifier module according to claim 14 , wherein the second bias-reducing circuit includes a second constant current circuit configured to output a second constant current, and wherein when the control current is greater than the second constant current, and a current corresponding to the difference between the second constant current and the control current is extracted from between the first constant current circuit and the fifth resistor.
for amplifiers using field-effect devices (H03F1/526 takes precedence) · CPC title
with field-effect devices (H03F3/195 takes precedence) · CPC title
with semiconductor devices only · CPC title
in integrated circuits · CPC title
the amplifier comprising circuitry for protection against overload · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.