Carbon nanotube semiconductor devices and deterministic nanofabrication methods

Patent metadata

Field	Value
Publication number	US-9240552-B2
Application number	US-201113977219-A
Country	US
Kind code	B2
Filing date	Dec 27, 2011
Priority date	Dec 27, 2011
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

Embodiments of the invention provide transistor structures and interconnect structures that employ carbon nanotubes (CNTs). Further embodiments of the invention provide methods of fabricating transistor structures and interconnect structures that employ carbon nanotubes. Deterministic nanofabrication techniques according to embodiments of the invention can provide efficient routes for the large-scale manufacture of transistor and interconnect structures for use, for example, in random logic and memory circuit applications.

First claim

We claim:

1. A structure comprising,
an array of assembly regions, wherein the array comprises at least two columns of assembly regions, wherein a first and a second column of the at least two columns of assembly regions each comprise at least two assembly regions, wherein the first column of assembly regions is separated from the second column of assembly regions by a first distance, wherein assembly regions within a column are separated from a nearest proximate assembly region by a second distance, and wherein the first distance is not the same as the second distance,
at least two carbon nanotubes wherein a first and a second carbon nanotube of the at least two carbon nanotubes have ends, wherein a first end of the first carbon nanotube is in direct contact with a first assembly region of the at least two assembly regions of the first column and a second end of the first carbon nanotube is in direct contact with a second assembly region of the at least two assembly regions of the second column, and wherein a first end of a second carbon nanotube is in direct contact with a third assembly region in the first column and a second end of the second carbon nanotube is in direct contact with a fourth assembly region in the second column, and
at least two source regions and at least two drain regions wherein a first source region of the at least two source regions is in contact with the first end of the first carbon nanotube, a second source region of the at least two source regions is in contact with the first end of the second carbon nanotube, a first drain region of the at least two drain regions is in contact with a second end of the first carbon nanotube, and a second drain region of the at least two drain regions is in contact with the second end of the second carbon nanotube.

2. The device of claim 1 wherein the first, second, third and fourth assembly regions comprise polysilicon or doped polysilicon wherein the polysilicon or doped polysilicon comprises carbon, nitrogen, and oxygen.

3. The device of claim 1 wherein the first, second, third and fourth assembly regions comprise a metal and a second substance that is selected from the group consisting of sulfur, nitrogen, and combinations thereof.

4. The device of claim 1 wherein the first, second, third and fourth assembly regions comprise a first metal selected from the group consisting of gold, silver, copper, cobalt, nickel, palladium, platinum, and combinations thereof.

5. The device of claim 4 wherein the first, second, third and fourth assembly regions comprise a second metal that is different from the first metal and selected from the group consisting of nickel and cobalt.

6. The device of claim 1 additionally comprising a first and a second gate dielectric region and a first and second gate electrode region wherein the first gate dielectric region is proximate to the first carbon nanotube, the second gate dielectric region is proximate to the second carbon nanotube, the first gate dielectric regions is between the first carbon nanotube and the first gate electrode region, and the second gate dielectric region is between the second carbon nanotube and the second gate electrode region.

7. The device of claim 1 wherein the at least two carbon nanotubes are single-walled semiconducting carbon nanotubes.

8. The device of claim 1 wherein a gate dielectric material is disposed on the first and the second carbon nanotube and a gate electrode is disposed on the gate dielectric material.

9. The device of claim 1 wherein a photo patternable low-k dielectric material is disposed on the carbon nanotube.

10. A computing device comprising,
a motherboard,
a communication chip mounted on the motherboard, and
a processor mounted on the motherboard, the processor comprising transistors, the transistors comprising:
an array of assembly regions, wherein the array comprises at least two columns of assembly regions, wherein a first and a second column of the at least two columns of assembly regions each comprise at least two assembly regions, wherein the first column of assembly regions is separated from the second column of assembly regions by a first distance, wherein assembly regions within a column are separated from a nearest proximate assembly region by a second distance, and wherein the first distance is not the same as the second distance,
at least two carbon nanotubes wherein a first and a second carbon nanotube of the at least two carbon nanotubes have ends, wherein a first end of the first carbon nanotube is in direct contact with a first assembly region of the at least two assembly regions of the first column and a second end of the first carbon nanotube is in direct contact with a second assembly region of the at least two assembly regions of the second column, and wherein a first end of a second carbon nanotube is in direct contact with a third assembly region in the first column and a second end of the second carbon nanotube is in direct contact with a fourth assembly region in the second column, and
at least two source regions and at least two drain regions wherein a first source region of the at least two source regions is in contact with the first end of the first carbon nanotube, a second source region of the at least two source regions is in contact with the first end of the second carbon nanotube, a first drain region of the at least two drain regions is in contact with a second end of the first carbon nanotube, and a second drain region of the at least two drain regions is in contact with the second end of the second carbon nanotube,
a conducting region in electrical contact with the at least one carbon nanotube disposed at the second end of the via.

11. The device of claim 10 wherein the first, second, third and fourth assembly regions comprise polysilicon or doped polysilicon wherein the polysilicon or doped polysilicon comprises carbon, nitrogen, and oxygen.

12. The device of claim 10 wherein the first, second, third and fourth assembly regions comprise a metal and a second substance that is selected from the group consisting of sulfur, nitrogen, and combinations thereof.

13. The device of claim 10 wherein the first, second, third and fourth assembly regions comprise a first metal selected from the group consisting of gold, silver, copper, cobalt, nickel, palladium, platinum, and combinations thereof.

14. The device of claim 13 wherein the first, second, third and fourth assembly regions comprise a second metal that is different from the first metal and selected from the group consisting of nickel and cobalt.

15. The device of claim 10 additionally comprising a first and a second gate dielectric region and a first and second gate electrode region wherein the first gate dielectric region is proximate to the first carbon nanotube, the second gate dielectric region is proximate to the second carbon nanotube, the first gate dielectric regions is between the first carbon nanotube and the first gate electrode region, and the second gate dielectric region is between the second carbon nanotube and the second gate electrode region.

16. The device of claim 10 wherein the at least two carbon nanotubes are single-walled semiconducting carbon nanotubes.

17. The device of claim 10 wherein a gate dielectric material is disposed on the first and the second carbon nanotube and a gate electrode is disposed on the gate dielectric material.

Assignees

• Wong Lawrence D
• Clendenning Scott B
• Michalak David J
• Intel Corp

Inventors

• Wong Lawrence D
• Clendenning Scott B
• Michalak David J

Classifications

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011 Primary

  comprising FinFETs · CPC title

• B82B3/0047 Primary

  Bonding two or more elements · CPC title

• H01L51/0048 Primary

  Electricity · mapped topic

• H01L27/1211

  Electricity · mapped topic