Wordline resistance reduction method and structure in an integrated circuit memory device

Patent metadata

Field	Value
Publication number	US-9240418-B2
Application number	US-96137910-A
Country	US
Kind code	B2
Filing date	Dec 6, 2010
Priority date	Apr 29, 2008
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.

First claim

What is claimed is:

1. A wordline structure, comprising:
a plurality of wordlines formed to include an ONO layer that is formed parallel to and directly contacting a substrate, the substrate comprising a plurality of source/drain regions having a first impurity implantation dosage; and
a plurality of respective oxide spacers disposed above respective source/drain regions of the plurality of source/drain regions and between wordlines to provide an insulation between adjacent wordlines, wherein each respective oxide spacer comprises a depression formed on a surface of the respective oxide spacer, wherein each respective oxide spacer contacts two adjacent wordlines to fill a space between the two adjacent wordlines, wherein the plurality of wordlines comprise a first salicide are formed by a first salicidation process while shielding other regions from being subjected to the same first salicidation process, and wherein a peripheral region adjacent to the plurality of wordlines has a second impurity implantation dosage that is greater than the first impurity implantation dosage, and comprises a second salicide formed by a different second salicidation process, wherein said first salicide has a first thickness that is greater than a second thickness of said second salicide.

2. The wordline structure of claim 1 , wherein the salicidation process of the plurality of wordlines reduces resistance formed on the plurality of wordlines.

3. The wordline structure of claim 1 , wherein the salicidation process comprises:
respective oxide spacers formed in between a plurality of columns of polycrystalline silicon to provide an insulation between adjacent ones of the wordlines;
respective recesses formed in the plurality of columns of the polycrystalline silicon by selectively etching top surfaces of the plurality of columns, wherein the respective recesses are filled with a transition metal or a metal.

4. The wordline structure of claim 3 , wherein the polycrystalline silicon and the transition metal or metal are annealed until the salicidation process is completed.

5. The wordline structure of claim 3 , wherein the transition metal comprises one of cobalt, nickel, platinum, titanium and tungsten.

6. The wordline structure of claim 3 , wherein a chemical-mechanical planarization process is utilized when the metal is used.

7. A wordline structure, comprising:
a plurality of wordlines formed to include an ONO layer that is formed parallel to and directly contacting a substrate, the substrate comprising a plurality of source/drain regions having a first impurity implantation dosage;
a spacer material disposed above respective source/drain regions of the plurality of source/drain regions and deposited between each of the plurality of wordlines, wherein each respective spacer material comprises a depression formed on a surface of the respective spacer material, wherein a first spacer material contacts two adjacent wordlines to fill a space between the two adjacent wordlines; and
a transition metal deposited on each of the plurality of wordlines, wherein the transition metal is annealed to salicide the plurality of wordlines comprising a first silicide by a first salicidation process, and wherein other regions are not subjected to the same first salicidation process, and wherein a peripheral region adjacent to the plurality of wordlines has a second impurity implantation dosage that is greater than the first impurity implantation dosage, and comprises a second salicide formed by a different second salicidation process, wherein said first silicide has a first thickness that is greater than a second thickness of said second salicide.

8. The wordline structure of claim 7 , wherein the spacer material comprises one of oxide, nitride, and other insulating material.

9. The wordline structure of claim 7 , wherein the transition metal comprises one of cobalt, nickel, platinum, titanium and tungsten.

10. The wordline structure of claim 7 , wherein the transition metal is deposited on the plurality of wordlines to fill recesses between each spacer material.

11. The wordline structure of claim 7 , wherein the salicides of plurality of wordlines are thicker than the salicides of at least one of the other regions.

12. The wordline structure of claim 7 , wherein the salicidation process of the plurality of wordlines reduces resistance formed on the plurality of wordlines.

13. The wordline structure of claim 7 , wherein the salicidation process comprises:
respective oxide spacers formed in between a plurality of columns of polycrystalline silicon to provide an insulation between adjacent ones of the wordlines;
respective recesses formed in the plurality of columns of the polycrystalline silicon by selectively etching top surfaces of the plurality of columns, wherein the respective recesses are filled with a transition metal or a metal.

Assignees

• Fang Shenqing
• Choi Jihwan
• Wang Connie
• Kim Eunha
• Cypress Semiconductor Corp

Inventors

• Fang Shenqing
• Choi Jihwan
• Wang Connie
• Kim Eunha

Classifications

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/0213

  providing different silicide thicknesses on gate electrodes and on source regions or drain regions · CPC title

• H10D30/0212

  using self-aligned silicidation · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title