Semiconductor memory device with a selection transistor having same shape and size as a memory cell transistor

Patent metadata

Field	Value
Publication number	US-9240221-B2
Application number	US-201314080694-A
Country	US
Kind code	B2
Filing date	Nov 14, 2013
Priority date	Jan 16, 2008
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a plurality of first sub-memory arrays; and
a main bit line connected to the plurality of first sub-memory arrays, wherein:
each of the plurality of first sub-memory arrays includes:
a pair of cell transistors that are adjacent along a first direction;
a pair of memory cells, each of the pair of memory cells including only one of the pair of cell transistors;
a sub-bit line connected to the pair of memory cells;
a ground line; and
a selection transistor connecting the sub-bit line to the main bit line, and having an active region,

the active region of the selection transistor has a same shape and size as an active region of the pair of cell transistors,
the pair of cell transistors are connected to the sub-bit line in parallel between the sub-bit line and the ground line,
the main bit line and the sub-bit line run in the first direction,
the ground line runs in a second direction perpendicular to the first direction,
the sub-bit line overlaps, in planar view, the active region of the selection transistor and the active region of the pair of cell transistors, and
the ground line overlaps, in planar view, the active region of the pair of cell transistors.

2. The semiconductor memory device of claim 1 , wherein a gate of the selection transistor has a same shape and size as that of the pair of cell transistors.

3. The semiconductor memory device of claim 1 , wherein:
each of the plurality of first sub-memory arrays further includes a discharge transistor connected to the sub-bit line, and
an active region of the discharge transistor has a same shape and size as that of the pair of cell transistors.

4. The semiconductor memory device of claim 1 , wherein:
the selection transistor comprises a plurality of active regions, and
each of the plurality of active regions of the selection transistor has a same shape and size as that of the pair of cell transistors.

5. The semiconductor memory device of claim 1 , further comprising a sense amplifier connected to the main bit line.

6. The semiconductor memory device of claim 5 , further comprising:
a second main bit line connected to the sense amplifier; and
a plurality of second sub-memory arrays,
wherein the second main bit line is connected to the plurality of second sub-memory arrays.

7. The semiconductor memory device of claim 1 , further comprising a local sense amplifier connecting the selection transistor to the main bit line.

8. The semiconductor memory device of claim 7 , wherein a transistor constituting the local sense amplifier has a same polarity as that of the pair of cell transistors.

9. The semiconductor memory device of claim 7 , wherein at least two of the plurality of first sub-memory arrays share the local sense amplifier.

10. The semiconductor memory device of claim 7 , wherein:
the local sense amplifier comprises a plurality of active regions, and
each of the plurality of active regions of the local sense amplifier has a same shape and size as that of the pair of cell transistors.

Assignees

• Panasonic Corp
• Socionext Inc

Inventors

• Terada Yutaka
• Agata Yasuhiro
• Abe Wataru
• Kurata Masakazu
• Misumi Kenji

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C5/06 Primary

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• H01L27/0207

  Electricity · mapped topic