Method of repeater chip

Patent metadata

Field	Value
Publication number	US-9239900-B2
Application number	US-201414534509-A
Country	US
Kind code	B2
Filing date	Nov 6, 2014
Priority date	Feb 20, 2013
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A design method of a repeater chip is provided, the repeater chip designed by using the method can implement interconnection among nodes, and implement packet sequence receiving, classifying, storing, forwarding, sorting, and transmitting functions of the repeater chip, thereby implementing effective extension of a high-speed transmission link among the nodes, so as to reduce hardware design difficulties and design risks. The structure of the repeater chip is formed by: an interface detecting unit, a sequence storing unit, a sequence forwarding unit, a sequence determining unit, and a sequence sorting unit.

First claim

The invention claimed is:

1. A design method of a repeater chip, comprising:
the repeater chip is used to implement interconnections among nodes, and implement a packet sequence receiving, classifying, storing, forwarding, sorting, and transmitting functions of the repeater chip, thereby implementing an effective extension of a high-speed transmission link among the nodes, so as to reduce hardware design difficulties and design risks, and a structure of the repeater chip comprises: an interface detecting unit, a sequence storing unit, a sequence forwarding unit, a sequence determining unit, and a sequence sorting unit, wherein:
for the interface detecting unit, according to features of a transmission link of a repeater chip application system, a clock detecting unit and a data detecting unit are designed in the interface detecting unit; in a power-on initial period of the repeater chip application system, the transmission link automatically detects connectivity of a link between an interconnection component and the repeater chip, and if a connectivity problem exists, a redundancy link is used to replace a failed link;
for the sequence storing unit, the sequence storing unit is implemented by using an FIFO according to function features of the repeater chip, that is, to store packets received by a PORT-L port or a PORT-R port, and in order to improve a performance of the repeater chip, multiple groups of FIFO storing units are implemented respectively according to different packet types of the received packets, so as to store various types of packets, wherein the packet types are distinguished by using the sequence determining unit;
for the sequence forwarding unit, a sequence of the received packet, after being stored by the sequence storing unit, is forwarded by the packet sequence forwarding unit, wherein the different packet types of the received packets are forwarded by using different channels, thereby improving an execution efficiency;
for the sequence determining unit, to improve the performance of the repeater chip, the sequence determining unit is designed to distinguish effective packets from ineffective packets, and classify the effective packets according to respective types, thereby improving a packet sequence processing efficiency of the repeater chip; and
for the sequence sorting unit, the different types of packets, after being forwarded, are sorted by the sequence sorting unit according to an order of packet transmission and a quantity requirement of the same packets, and then are sent through the PORT-R port or the PORT-L port and transmitted to another node.

2. The design method according to claim 1 , wherein:
a design structure of the interface detection unit implements detection functions of a clock and a data channel in the interface detection unit according to features of design requirements of high reliability of a multi-path computer system, and when the connectivity of a connectivity of a link of a channel is detected as a failed one, a redundancy design is used to replace the failed channel detected, thereby achieving one of the design requirements of high reliability.

3. The design method according to claim 1 , wherein:
a design structure of the sequence storing unit utilizes designs of various types of storage components according to features of design requirements of high performance and high transmission bandwidth of a multi-path computer system, so as to implement respective processing of different packet types, thereby improving performance of the packet processing.

4. The design method according to claim 1 , wherein:
a design structure of the sequence forwarding unit adopts different transmission channels to respectively implement forwarding of different packet types, thereby implementing a high-efficient processing of packets.

5. The design method according to claim 1 , wherein:
a design structure of the sequence determining unit adopts a packet screening manner to implement classification of effective packets and ineffective packets, thereby implementing a classified management of the effective packets.

6. The design method according to claim 1 , wherein:
a design structure of the sequence sorting unit performs sorting based on transmissions of different types of packets and analyzing a transmission quantity of packets of the same type according to requirements of system transmission characteristics.

Assignees

• Inspur Electronic Information Industry Co Ltd
• Inspur Electronic Information Industry Co Ltd

Inventors

• Wang Endong
• Hu Leijun
• Li Rengang

Classifications

• G06F30/30 Primary

  Circuit design · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/00

  Computer-aided design [CAD] · CPC title

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title