Nonvolatile memory device and program method thereof

Patent metadata

Field	Value
Publication number	US-9239782-B2
Application number	US-201313830310-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	May 17, 2012
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

Disclosed is a nonvolatile memory device which includes a nonvolatile memory including a plurality of LSB and MSB pages at a plurality of wordlines; and a controller controlling the nonvolatile memory. The controller controls the nonvolatile memory such that an LSB program operation on a first wordline of the plurality of wordlines is programmed and then an LSB program operation on a second wordline of the plurality of wordlines is programmed. When the LSB program operation on the second wordline is performed, the nonvolatile memory stores information about LSB data programmed at the first wordline at a spare area of the second wordline.

First claim

What is claimed is:

1. A nonvolatile memory device, comprising:
a nonvolatile memory including a plurality of wordlines; and
a controller configured to control the nonvolatile memory,
wherein the controller controls the nonvolatile memory such that an LSB program operation on a first wordline of the plurality of wordlines is performed and then an LSB program operation on a second wordline of the plurality of wordline is performed; and
wherein while the LSB program operation on the second wordline is performed, the nonvolatile memory stores information about LSB data programmed at the first wordline in spare memory cells on the second wordline in a spare area of the nonvolatile memory,
wherein the information indicates the LSB data is invalid when the LSB data programmed at the first word line is invalid, and
wherein if a power-off occurred during a MSB program operation on the first word line, the controller controls the nonvolatile memory to skip a LSB recovery operation on the LSB data stored at the first wordline when the information indicates the LSB data programmed at the first wordline is invalid.

2. The nonvolatile memory device of claim 1 , wherein each wordline comprises an LSB page and an MSB page, and wherein if a logical address of the LSB data programmed at the first wordline is equal to a logical address of data programmed at the second wordline, the nonvolatile memory stores the information indicating that the LSB data programmed at the first wordline is invalid, at the spare area of the second wordline.

3. The nonvolatile memory device of claim 2 , wherein after the LSB program operation on the second wordline is performed, the nonvolatile memory performs an MSB program operation on the first word line.

4. The nonvolatile memory device of claim 3 , wherein if the nonvolatile memory stores information indicating that the LSB data programmed at the first wordline is invalid, the nonvolatile memory does not perform a backup operation on the LSB data stored at the first wordline.

5. The nonvolatile memory device of claim 1 , wherein if a logical address of data programmed at the first page is not equal to a logical address of data programmed at the second page, the nonvolatile memory stores address information, indicating a backup location of the LSB data programmed at the first page, at memory cells in a spare area of the second wordline.

6. The nonvolatile memory device of claim 5 , wherein after the LSB program operation on the second wordline is performed the nonvolatile memory backs up the LSB data programmed at the first wordline to a location indicated by the address information before an MSB program operation on the first wordline is performed by the controller.

7. The nonvolatile memory device of claim 5 , wherein the controller comprises:
a mapping table that manages logical addresses and physical addresses associated with a page to be programmed of the plurality of wordlines; and
an LSB recovery manager which judges whether a logical address of write-requested data is equal to a logical address of a programmed page, based on the mapping table.

8. The nonvolatile memory device of claim 7 , wherein the mapping table further includes information indicating whether data stored at the programmed page is LSB data, and wherein: when a logical address of the write-requested data is equal to a logical address of a selected one of programmed pages, the LSB recovery manager judges whether the selected page is an LSB page, based on the mapping table.

9. The nonvolatile memory device of claim 8 , wherein the LSB recovery manager judges whether a page at which the write-requested data is to be stored is an LSB page, based on the mapping table.

10. The nonvolatile memory device of claim 1 , wherein the controller controls the nonvolatile memory to perform a program operation by a unit formed of a plurality of pages.

11. A program method of a nonvolatile memory supporting multilevel cell storage, the program method comprising:
a controller of the nonvolatile memory receiving and writing first write-requested data to the nonvolatile memory and then receiving second write-requested data;
the controller judging whether a LSB page of the first write-requested data is invalidated, based on the second write-requested data;
the controller storing information, indicating that the LSB page of the first write-requested data is invalid, at a spare area of a page in the nonvolatile memory at which the second write-requested data is to be programmed; and
if a power-off occurred, the controller skipping a LSB recovery operation on the LSB page of the first write-requested data when the information indicates the LSB page of the first write-requested data is invalid.

12. The program method of claim 11 , further comprising: storing location information, at which the LSB page of the first write-requested data is to be backed up, at a spare area of the page where the second write-requested data is to be programmed, when a logical address of the second write-requested data is not equal to a logical address of the LSB page of the first write-requested data.

13. The program method of claim 11 , further comprising: comparing a logical address of the second write-requested data with a logical address managed at a mapping table.

14. A nonvolatile memory device, comprising: a memory block including:
a first wordline connected to a first plurality of nonvolatile memory cells;
a second wordline connected to a second plurality of nonvolatile memory cells;
a third wordline connected to a third plurality of nonvolatile memory cells;
a fourth wordline connected to a fourth plurality of nonvolatile memory cells;
a first bitline in a data storage region of the memory block and connected to one nonvolatile memory cell in each of first, second, third, and fourth pluralities of nonvolatile memory cells;
a second bitline in a spare region of the memory block and connected to one nonvolatile memory cell in each of first, second, third, and fourth pluralities of nonvolatile memory cells; and
a controller configured to control the nonvolatile memory, wherein the controller controls the nonvolatile memory such that:
a first LSB program operation is performed on the memory cells connected to the first wordline in the data storage region; and
then an second LSB program operation is performed on the memory cells connected to the second wordline in the data storage region;
wherein while the second LSB program operation is being performed, the nonvolatile memory stores information about LSB data programmed at the first wordline in the spare region of the memory block,
wherein the information indicates the LSB data is invalid when the LSB data stored at the first word line is invalid, and
wherein if a power-off occurred, the controller controls the nonvolatile memory to skip a LSB recovery operation on the LSB data stored at the first wordline when the information indicates the LSB data programmed at the first wordline is invalid.

15. The nonvolatile memory device of claim 14 , wherein the controller further controls the nonvolatile memory such that:
after the second LSB program operation is performed, then a first MSB program operation is performed on the memory cells connected to the first wordline in the data storage region; and
then a third LSB program operation is performed on the memory cells connected to the third wordline in the data storage region; and
then a second MSB program operation is performed on the memory cells connected to the second wordline in the data storage region.

16. The nonvolatile

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Woo-Young

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C16/22

  Safety or protection circuits preventing unauthorised or accidental access to memory cells · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/34 Primary

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title