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System for efficient caching of swap I/O and/or similar I/O pattern(s)
US9239679B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9239679-B2 |
| Application number | US-201414145943-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 1, 2014 |
| Priority date | Dec 19, 2013 |
| Publication date | Jan 19, 2016 |
| Grant date | Jan 19, 2016 |
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Abstract
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An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache may comprise one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. The controller is connected to the memory and configured to (A) process normal read/write operations in a first mode and (B) process special read/write operations in a second mode by (i) tracking a write followed by read condition on each of said cache windows and (ii) discarding data on the cache-lines associated with the cache windows after completion of the write followed by a read condition on the cache-lines.
First claim
Opening claim text (preview).
The invention claimed is: 1. An apparatus comprising: a memory configured to (i) implement a cache and (ii) store meta-data, said cache comprising one or more cache windows, each of said one or more cache windows comprising a plurality of cache-lines configured to store information; and a controller connected to said memory and configured to (A) process normal read/write operations in a first mode and (B) process special read/write operations in a second mode by (i) tracking a w…
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Classifications
- G06F3/06Primary
Physics · mapped topic
- G06F12/0804Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9239679B2 cover?
- An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache may comprise one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. The controller is connected to the memory and configured to (A) process normal read/write operations in a fi…
- Who is the assignee on this patent?
- Lsi Corp, Avago Technologies General Ip
- What technology area does this patent fall under?
- Primary CPC classification G06F3/06. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).