Flash memory controller and associated control method
US-2024377989-A1 · Nov 14, 2024 · US
US9239607B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9239607-B2 |
| Application number | US-201113334729-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 22, 2011 |
| Priority date | Dec 22, 2011 |
| Publication date | Jan 19, 2016 |
| Grant date | Jan 19, 2016 |
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Official abstract text for this publication.
In one embodiment, the present invention includes a method for obtaining file information regarding a file to be downloaded from a remote location to a computing device, creating at least one empty file in a destination storage based on the file information and communicating block information regarding the empty file to a network interface, and receiving a data packet of the file in the network interface and directly sending a payload of the data packet from the network interface to the destination storage according to the block information, while a host processor of the computing device is in a low power state. Other embodiments are described and claimed.
Opening claim text (preview).
What is claimed is: 1. At least one non-transitory computer accessible medium comprising instructions that when executed cause a computing device to: obtain file information regarding a file to be downloaded from a remote location to a computing device; create at least one empty file in a destination storage of the computing device based on the file information and communicate block information regarding the at least one empty file to a network interface of the computing device; and receive a data packet of the file in the network interface and directly send a payload of the data packet from the network interface to a security processor of the computing device interposed between the network interface and the destination storage according to the block information, while a host processor of the computing device is in a low power state. 2. The at least one non-transitory computer accessible medium of claim 1 , wherein the instructions further cause the computing device to forward a control header of the data packet to the host processor of the computing device. 3. The at least one non-transitory computer accessible medium of claim 1 , wherein the instructions further cause the computing device to use a file system of the computing device to create the at least one empty file. 4. The at least one non-transitory computer accessible medium of claim 1 , wherein the file comprises audio information, and the destination storage comprises a random access memory (RAM) disk of the computing device. 5. The at least one non-transitory computer accessible medium of claim 1 , wherein the instructions further cause the computing device to directly send the payload from the network interface to the destination storage without intermediately storing the payload in a system memory of the computing device. 6. The at least one non-transitory computer accessible medium of claim 5 , wherein the instructions further cause the computing device to maintain the system memory in a low power state while the file is downloaded to the computing device. 7. The at least one non-transitory computer accessible medium of claim 1 , wherein the instructions further cause the computing device to power down a core domain of a system on a chip (SoC) of the computing device while directly sending the payload from the network interface to the destination storage. 8. The at least one non-transitory computer accessible medium of claim 7 , wherein the instructions further cause the computing device to power a device domain and an interconnect domain of the SoC while directly sending the payload from the network interface to the destination storage, the device domain including the network interface. 9. The at least one non-transitory computer accessible medium of claim 8 , wherein the instructions further cause the computing device to power the core domain of the SoC while the network interface receives at least some data packets of the file, and perform processing unrelated to the file in the core domain. 10. A system on a chip (SoC) comprising: a core domain including a plurality of cores to independently execute instructions; an interconnect domain to couple the core domain to a plurality of intellectual property (IP) logics of a device domain; and the device domain including a source IP logic, the source IP logic to couple to a network to receive a file requested by a user, the source IP logic to directly transfer payload data of data packets of the file to a destination IP logic via a security processor of the device domain, without communication of the payload data to the core domain and responsive to communication of direct data transfer setup information received from the core domain, while at least a portion of the core domain is in a low power state. 11. The SoC of claim 10 , wherein the direct data transfer of payload is through the interconnect domain and bypasses the core domain. 12. The SoC of claim 10 , wherein the source IP logic is to communicate control information of at least one of the data packets of the file to the core domain. 13. The SoC of claim 12 , wherein the core domain is to cause an empty file to be created within the destination IP logic responsive to an application request. 14. The SoC of claim 13 , wherein the core domain is to communicate file block information associated with the empty file and corresponding to the direct data transfer setup information to the source IP logic to enable the source IP logic to directly transfer the payload data of data packets of the file to the destination IP logic. 15. A system comprising: a processor to execute instructions; a wireless transceiver to transmit and receive instructions wirelessly; a source agent to couple to a network to receive a file requested by a client application executing on the processor, wherein the source agent is to communicate an exception associated with receipt of the file to the processor, and the processor is to handle the exception and provide additional block information to the source agent responsive to the exception when the exception corresponds to a request for additional storage space for the file; a destination agent coupled to the source agent to store the file; and at least one storage medium including instructions that enable the system to obtain file information regarding the file, communicate the file information to a file system of the system via the client application, create at least one file in the destination agent based on the file information via the file system and communicate block information regarding the at least one file to the source agent, and to thereafter receive a data packet of the file in the source agent, provide a control portion of the data packet to the processor to enable the processor to perform network protocol stack processing for the file, and provide a data portion of the data packet directly to the destination agent according to the block information via a bypass path that couples the source agent and the destination agent while bypassing the processor and a system memory while the processor is in a low power state. 16. The system of claim 15 , wherein the source agent is to provide data portions of additional data packets of the file directly to the destination agent according to the additional block information via the bypass path.
Details of memory controller · CPC title
Power saving characterised by the action undertaken · CPC title
Parsing or analysis of headers · CPC title
for reducing power consumption or coping with limited storage space, e.g. in mobile devices (saving storage space on storage devices G06F3/0608; power saving in storage systems G06F3/0625) · CPC title
Power saving in storage systems · CPC title
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