Self-adjustable current source control circuit for linear regulators

Patent metadata

Field	Value
Publication number	US-9239584-B2
Application number	US-201314084538-A
Country	US
Kind code	B2
Filing date	Nov 19, 2013
Priority date	Nov 19, 2013
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A self-adjustable current source control circuit utilizes a replica output stage, a sink current source that generates a reference current, and a negative feedback circuit to generate a sink current between a linear regulator output terminal and ground only when a load circuit connected to the linear regulator is in a low power consuming state. The replica output stage includes an 1:N scaled replica of the linear regulator's NMOS (or NPN) output stage transistor, and the negative feedback circuit utilizes two PMOS (or PNP) negative feedback transistors having the same N:1 size ratio and connected as a common gate amplifier, whereby one of the two negative feedback transistors turns on to draw the desired sink current from the regulator output terminal only when the load current falls below N times the reference current (i.e., only the load current is drawn through the output stage transistor during high load current conditions).

First claim

The invention claimed is:

1. A system including a regulator circuit and a load circuit connected to an output terminal of the regulator circuit, wherein the regulator circuit comprises:
an output stage transistor connected between an unregulated voltage supply and the output terminal;
means for generating an output stage gate voltage that is supplied to the gate terminal of the output stage transistor such that said output stage transistor generates a regulated output voltage on the output terminal; and
a self-adjustable current source control circuit including:
a replica output stage transistor connected between the unregulated voltage supply and a replica output node;
a sink current source coupled between the replica output stage transistor and a low voltage source;
a first negative feedback transistor connected between the replica output node and the sink current source; and
a second negative feedback transistor connected between the output terminal and the low voltage source,
wherein the gate terminals of the first and second feedback transistors are connected to the sink current source.

2. The system of claim 1 ,
wherein the output stage transistor comprises a first NMOS transistor having a gate terminal connected to receive the output stage gate voltage, a drain terminal connected to the unregulated voltage supply and source terminal connected to the output terminal,
wherein the replica output stage transistor comprises a second NMOS transistor having a gate terminal connected to receive the output stage gate voltage, a drain terminal connected to the unregulated voltage supply and source terminal connected to the replica output node, and
wherein the second NMOS transistor is a 1:N scale replica of the first NMOS transistor, where N is a real number/integer greater than 1.

3. The system of claim 2 ,
wherein the first negative feedback transistor comprises a first PMOS transistor having a gate terminal and a drain terminal connected to the sink current source, and a source terminal connected to the replica output node,
wherein the second negative feedback transistor comprises a second PMOS transistor having a gate terminal connected to the sink current source, a source terminal connected to the output terminal, and a drain terminal connected to the low voltage source,
wherein the first PMOS transistor is a 1:N scale replica of the second PMOS transistor.

4. The system of claim 3 , wherein said means for generating the output stage gate voltage comprises a differential amplifier having a first input terminal connected to receive a feedback voltage, a second input terminal connected to receive an externally supplied reference voltage, and an output terminal connected to the gate terminal of the first NMOS transistor.

5. The system of claim 4 , wherein said means for generating the output stage gate voltage further comprises a voltage divider circuit including first and second resistors coupled between the output terminal and the low voltage source, wherein the first input terminal of the differential amplifier is connected to a feedback node disposed between the first and second resistors.

6. The system of claim 5 , wherein said differential amplifier comprises an operational amplifier having an inverting input terminal connected to receive said feedback voltage and a non-inverting input terminal connected to receive said externally supplied reference voltage.

7. The system of claim 1 ,
wherein the output stage transistor comprises a first NPN transistor having a base terminal connected to receive the output stage gate voltage, a collector terminal connected to the unregulated voltage supply and an emitter terminal connected to the put terminal,
wherein the replica output stage transistor comprises a second NPN transistor having a base terminal connected to receive the output stage gate voltage, a collector terminal connected to the unregulated voltage supply and an emitter terminal connected to the replica output node, and
wherein the second NPN transistor is a 1:N scale replica of the first NPN transistor, where N is a real number/integer greater than 1.

8. The system of claim 7 ,
wherein the first negative feedback transistor comprises a first PNP transistor having a base terminal and a collector terminal connected to the sink current source, and an emitter terminal connected to the replica output node,
wherein the second negative feedback transistor comprises a second PNP transistor having a base terminal connected to the sink current source, an emitter terminal connected to the output terminal, and a collector terminal connected to the low voltage source,
wherein the first PNP transistor is a 1:N scale replica of the second PNP transistor.

9. The system of claim 8 , wherein said means for generating the output stage gate voltage comprises a differential amplifier having a first input terminal connected to receive a feedback voltage, a second input terminal connected to receive an externally supplied reference voltage, and an output terminal connected to the base terminal of the first NPN transistor.

10. The system of claim 9 , wherein said means for generating the output stage gate voltage further comprises a voltage divider circuit including first and second resistors coupled between the output terminal and the low voltage source, wherein the first input terminal of the differential amplifier is connected to a feedback node disposed between the first and second resistors.

11. The system of claim 10 , wherein said differential amplifier comprises an operational amplifier having an inverting input terminal connected to receive said feedback voltage and a non-inverting input terminal connected to receive said externally supplied reference voltage.

12. The system of claim 1 , wherein the regulator circuit is a low dropout regulator circuit.

13. A linear regulator circuit for supplying a regulated voltage supply to a load circuit connected to an output terminal of the regulator circuit, wherein the regulator circuit comprises:
means for generating a regulated output voltage on the output terminal; and
a self-adjustable current source control circuit including:
means for generating a replica regulated output voltage on a replica output node;
a sink current source coupled between the replica output node and a low voltage source;
a first negative feedback transistor connected between the replica output node and the sink current source; and
a second negative feedback transistor connected between the output terminal and the low voltage source,
wherein the gate terminals of the first and second feedback transistors are connected to the sink current source.

14. The linear regulator circuit of claim 13 ,
wherein said means for generating a regulated output voltage on the output terminal comprises an output stage transistor connected between an unregulated voltage supply and the output terminal, and a differential amplifier circuit for generating an output stage gate voltage applied to a gate terminal of the output stage transistor, and
wherein said means for generating a replica regulated output voltage on the replica output node comprises a replica output stage transistor connected between the unregulated voltage supply and the replica output node and having a gate terminal connected to the gate terminal of the output stage transistor.

15. The linear regulator circuit of claim 14 ,
wherein the output stage transistor comprises a first NMOS transistor having a gate terminal connected to receive the output stage gate voltage, a drain terminal connected to the unregulated voltage supply

Assignees

• Tower Semiconductor Ltd

Inventors

• Lerner Valentin
• Pollak Danny

Classifications

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• G05F1/565

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title