Display device substrate and method for fabricating same, and display device

US9239484B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9239484-B2
Application numberUS-201113884356-A
CountryUS
Kind codeB2
Filing dateNov 2, 2011
Priority dateNov 10, 2010
Publication dateJan 19, 2016
Grant dateJan 19, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A thin film transistor substrate ( 20 a ) includes an insulating substrate ( 10 a ), a semiconductor layer ( 13 a ) provided on the insulating substrate ( 10 a ) and having a channel region (C), and a channel protection layer ( 25 ) provided in the channel region (C). The channel protection layer ( 25 ) is made of a multilayer film in which first insulating films and second insulating films are alternately layered. A relationship between a refractive index Ra of the first insulating film and a refractive index Rb of the second insulating film is Rb/Ra≧1.3.

First claim

Opening claim text (preview).

The invention claimed is: 1. A display device substrate, comprising: an insulating substrate; a gate electrode provided directly on the insulation substrate; a gate insulating film provided directly on the insulating substrate and the gate electrode; a semiconductor layer provided on the insulating substrate, directly provided on the gate insulating film, and including a channel region; and a channel protection layer provided in the channel region and made of an insulating material, wherein a fine projection/recess structure including recesses and projections is defined in a surface of the channel protection layer which faces away from the semiconductor layer. 2. The display device substrate of claim 1 , wherein a distance between adjacent ones of the projections or adjacent ones of the recesses of the projection/recess structure is 380 nm or less. 3. The display device substrate of claim 1 , wherein a height of the projection or a depth of the recess is 760 nm or more. 4. The display device substrate of claim 1 , wherein the semiconductor layer is a semiconductor layer of a thin film transistor. 5. The display device substrate of claim 1 , wherein the semiconductor layer defines an optical sensor. 6. A display device, comprising: the display device substrate of claim 1 ; a second display device substrate located to face the display device substrate; and a display medium layer provided between the display device substrate and the second display device substrate. 7. The display device of claim 6 , wherein the display medium layer is a liquid crystal layer.

Assignees

Inventors

Classifications

  • Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

  • Bottom-gate only TFTs · CPC title

  • having light shields · CPC title

  • of lateral bottom-gate TFTs comprising only a single gate · CPC title

  • reflector · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9239484B2 cover?
A thin film transistor substrate ( 20 a ) includes an insulating substrate ( 10 a ), a semiconductor layer ( 13 a ) provided on the insulating substrate ( 10 a ) and having a channel region (C), and a channel protection layer ( 25 ) provided in the channel region (C). The channel protection layer ( 25 ) is made of a multilayer film in which first insulating films and second insulating f…
Who is the assignee on this patent?
Kuniyoshi Tokuaki, Sharp Kk
What technology area does this patent fall under?
Primary CPC classification G02F1/136209. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).