Light emitting device and light emitting device array

US9236526B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9236526-B2
Application numberUS-201314062131-A
CountryUS
Kind codeB2
Filing dateOct 24, 2013
Priority dateNov 5, 2012
Publication dateJan 12, 2016
Grant dateJan 12, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A light emitting structure includes lower and upper semiconductor layers having different conductive types, and an active layer disposed between the lower and upper semiconductor layers. The light emitting structure is provided on the substrate. A first electrode layer provided on the upper semiconductor layer includes a first adhesive layer and a first bonding layer overlapping each other. A reflective layer is not provided between the first adhesive layer and the first bonding layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A light emitting device array, comprising: a substrate; a plurality of light emitting devices spaced from one another in a horizontal direction on the substrate; a conductive interconnection layer to connect the two light emitting devices among the plurality of light emitting devices; and a first insulating layer between the light emitting devices and the conductive interconnection layer, wherein respective light emitting devices comprise: a light emitting structure including lower and upper semiconductor layers having different conductive types, and an active layer provided between the lower and upper semiconductor layers; a first electrode layer provided on the upper semiconductor layer; and a second electrode layer provided on the lower semiconductor layer, wherein the conductive interconnection layer connects the first electrode layer of one of the two light emitting devices to the second electrode layer of the other of the two light emitting devices, wherein the first electrode layer includes a first adhesive layer and a first bonding layer overlapping each other, wherein a reflective layer is not provided between the first adhesive layer and the first bonding layer, wherein the conductive interconnection layer comprises a third adhesive layer and a third bonding layer overlapping each other, and wherein a reflective layer is not disposed between the third adhesive layer and the third bonding layer. 2. The light emitting device array according to claim 1 , wherein the conductive interconnection layer further comprises a third barrier layer on the third adhesive layer such that the third barrier layer contacts the third adhesive layer. 3. The light emitting device array according to claim 1 , further comprising a second insulating layer disposed between the first insulating layer and the light emitting devices. 4. The light emitting device array according to claim 3 , wherein at least one of the first and second insulating layers is a distributed Bragg reflector. 5. The light emitting device array according to claim 1 , wherein the first and second electrode layers of the two light emitting devices connected through the conductive interconnection layer, and the conductive interconnection layer are integrated with one another. 6. The light emitting device array according to claim 1 , wherein each light emitting device further comprises a conductive layer disposed between the upper semiconductor layer and the first electrode layer. 7. The light emitting device array according to claim 6 , wherein each light emitting device further comprises a current blocking layer spaced from the first insulating layer between the light emitting structure and the first electrode layer. 8. A light emitting device array, comprising: a substrate; a plurality of light emitting devices spaced from one another in a horizontal direction on the substrate; a conductive interconnection layer to connect the two light emitting devices among the plurality of light emitting devices; a first insulating layer between the light emitting devices and the conductive interconnection layer; and a second insulating layer disposed between the first insulating layer and the light emitting devices, wherein respective light emitting devices comprise: a light emitting structure including lower and upper semiconductor layers having different conductive types, and an active layer provided between the lower and upper semiconductor layers; a first electrode layer provided on the upper semiconductor layer; and a second electrode layer provided on the lower semiconductor layer, wherein the conductive interconnection layer connects the first electrode layer of one of the two light emitting devices to the second electrode layer of the other of the two light emitting devices, wherein the first electrode layer includes a first adhesive layer and a first bonding layer overlapping each other, wherein a reflective layer is not provided between the first adhesive layer and the first bonding layer, wherein the conductive interconnection layer comprises a third adhesive layer and a third bonding layer overlapping each other, and wherein a reflective layer is not disposed between the third adhesive layer and the third bonding layer. 9. The light emitting device array according to claim 8 , wherein at least one of the first and second insulating layers is a distributed Bragg reflector. 10. A light emitting device array, comprising: a substrate; a plurality of light emitting devices spaced from one another in a horizontal direction on the substrate; a conductive interconnection layer to connect the two light emitting devices among the plurality of light emitting devices; and a first insulating layer between the light emitting devices and the conductive interconnection layer, wherein respective light emitting devices comprise: a light emitting structure including lower and upper semiconductor layers having different conductive types, and an active layer provided between the lower and upper semiconductor layers; a first electrode layer provided on the upper semiconductor layer; and a second electrode layer provided on the lower semiconductor layer, wherein the conductive interconnection layer connects the first electrode layer of one of the two light emitting devices to the second electrode layer of the other of the two light emitting devices, wherein the first electrode layer includes a first adhesive layer and a first bonding layer overlapping each other, wherein a reflective layer is not provided between the first adhesive layer and the first bonding layer, wherein the conductive interconnection layer comprises a third adhesive layer and a third bonding layer overlapping each other, wherein a reflective layer is not disposed between the third adhesive layer and the third bonding layer, and wherein each light emitting device further comprises a conductive layer disposed between the upper semiconductor layer and the first electrode layer. 11. The light emitting device array according to claim 10 , wherein each light emitting device further comprises a current blocking layer spaced from the first insulating layer between the light emitting structure and the first electrode layer.

Assignees

Inventors

Classifications

  • containing nitrogen, e.g. GaN · CPC title

  • Current-blocking structures · CPC title

  • Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

  • Reflective coatings, e.g. dielectric Bragg reflectors · CPC title

  • H10H20/832Primary

    characterised by their material · CPC title

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What does patent US9236526B2 cover?
A light emitting structure includes lower and upper semiconductor layers having different conductive types, and an active layer disposed between the lower and upper semiconductor layers. The light emitting structure is provided on the substrate. A first electrode layer provided on the upper semiconductor layer includes a first adhesive layer and a first bonding layer overlapping each other. A r…
Who is the assignee on this patent?
Lg Innotek Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10H20/832. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 12 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).