Thin film transistor and method for producing same

Patent metadata

Field	Value
Publication number	US-9236488-B2
Application number	US-201214422002-A
Country	US
Kind code	B2
Filing date	Aug 23, 2012
Priority date	Aug 23, 2012
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A thin film transistor is equipped with a silicon substrate, a channel layer, a source electrode and a drain electrode. The channel layer, the source electrode and the drain electrode are arranged on the main surface of the silicon substrate. The channel layer is composed of multiple carbon nanowall thin films, wherein the multiple carbon nanowall thin films are arranged in parallel to each other between the source electrode and the drain electrode, one end of each of the multiple carbon nanowall thin films is in contact with the source electrode, and the other end of each of the multiple carbon nanowall thin films is in contact with the drain electrode. An insulating film and a gate electrode are arranged on the rear surface side of the silicon substrate.

First claim

What is claimed is:

1. A thin film transistor, comprising:
a silicon substrate having a main surface formed with a stripe-like or grid-like concave-convex configuration;
a channel layer formed of a plurality of carbon nanowall thin films which are disposed on a plurality of protruding portions along a length direction of the protruding portion of the concave-convex shape, and respectively grows in a normal direction of the silicon substrate;
a source electrode at least contacting a first side surface of each of the plurality of carbon nanowall thin films which is in parallel to a thickness direction of the carbon nanowall thin film;
a drain electrode disposed so as to be opposed to the source electrode in an in-plane direction of the carbon nanowall thin film, and at least contacting a second side surface of each of the plurality of carbon nanowall thin films which is opposite to the first side surface;
a gate electrode; and
an insulating film disposed between the plurality of carbon nanowall thin films and the gate electrode.

2. The thin film transistor of claim 1 , wherein:
the insulating film is disposed to be in contact with a surface opposite to the one main surface of the silicon substrate, and
the gate electrode is disposed to be in contact with the insulating film, and
the source electrode and the drain electrode are disposed along the length direction of the protruding portion of the concave-convex shape.

3. The thin film transistor of claim 1 , wherein:
the insulating film is disposed to be in contact with a third side surface of each of the plurality of carbon nanowall thin films which is in parallel to the thickness direction of the carbon nanowall thin film on an opposite side of a silicon substrate side, and
the gate electrode is disposed to be in contact with the insulating film, and
the source electrode and the drain electrode are disposed along the length direction of the protruding portion of the concave-convex shape.

4. The thin film transistor of claim 2 , wherein:
the source electrode is formed of a plurality of source electrode members provided corresponding to the plurality of carbon nanowall thin films, and each of the source electrode members is disposed to be at least in contact with the first side surface of the corresponding carbon nanowall thin film, and
the drain electrode is formed of a plurality of drain electrode members provided corresponding to the plurality of carbon nanowall thin films, and each of the drain electrode members is disposed to be at least in contact with the second side surface of the corresponding carbon nanowall thin film.

5. The thin film transistor of claim 1 , wherein:
the insulating film is formed of a plurality of gate insulating films which are provided corresponding to the plurality of carbon nanowall thin films and are disposed along the in-plane direction of the carbon nanowall thin film, and each of the gate insulating films at least contacts the corresponding carbon nanowall thin film, and
the gate electrode is formed of a plurality of gate electrode members provided corresponding to the plurality of gate insulating films, and each of the gate electrode members is disposed to be in contact with the corresponding gate insulating film, and
one of the source electrode and the drain electrode is disposed in the silicon substrate on the protruding portion side, and
the other one of the source electrode and the drain electrode is disposed on an opposite side of the silicon substrate side in the normal direction of the silicon substrate.

6. The thin film transistor of claim 1 , wherein:
the insulating film is formed of a plurality of gate insulating films which are provided corresponding to the plurality of carbon nanowall thin films and are disposed along the in-plane direction of the carbon nanowall thin film, and each of the gate insulating films at least contacts the corresponding carbon nanowall thin film, and
the gate electrode is formed of a plurality of gate electrode members provided corresponding to the plurality of gate insulating films, and each of the gate electrode members is disposed to be in contact with the corresponding gate insulating film, and
one of the source electrode and the drain electrode is formed of a plurality of first electrode members provided corresponding to the plurality of carbon nanowall thin films, and
the other one of the source electrode and the drain electrode is formed of a plurality of second electrode members provided corresponding to the plurality of carbon nanowall thin films, and
each of the plurality of first electrode members comprises an impurity region formed in a protruding portion which contacts the corresponding carbon nanowall thin film and a metal region disposed to be in contact with the impurity region, and
each of the plurality of second electrode members is in contact with a third side surface of the corresponding carbon nanowall thin film which is in parallel to the thickness direction of the corresponding carbon nanowall thin film and disposed on an opposite side of the silicon substrate side.

7. A production method for producing a thin film transistor which uses a plurality of carbon nanowall thin films as a channel layer, the production method comprising:
a first process of forming a concave-convex shape in stripe-like or grid-like concave-convex configurations on a main surface of a silicon substrate;
a second process of forming the plurality of carbon nanowall thin films on a plurality of protruding portions of the concave-convex shape along a length direction of the protruding portion;
a third process of forming a source electrode so as to at least contact a first side surface of each of the plurality of carbon nanowall thin films which is in parallel to a thickness direction of the carbon nanowall thin film;
a fourth process of forming a drain electrode disposed so as to be opposed to the source electrode in an in-plane direction of the carbon nanowall thin film and at least contact a second side surface of each of the plurality of carbon nanowall thin films which is opposite to the first side surface;
a fifth process of forming an insulating film so as to face the plurality of carbon nanowall thin films; and
a sixth process of forming a gate electrode so as to contact the insulating film.

8. The production method for producing the thin film transistor of claim 7 , further comprising:
a seventh process of removing the carbon nanowall thin films formed in a region other than a disposition region of the thin film transistor by plasma using oxygen gas.

9. The production method for producing the thin film transistor of claim 7 , further comprising:
an eighth process of processing the plurality of carbon nanowall thin films by plasma using hydrogen gas, wherein
the third process and the fourth process are performed following the eighth process.

Assignees

• Kawahara Toshio
• Okamoto Kazumasa
• Matsumoto Kazuhiko
• Utsunomiya Risa
• Matsuba Teruaki
• Matsumoto Hitoshi
• Univ Chubu Educational Foundation
• Univ Hokkaido Nat Univ Corp
• Univ Osaka
• Nissin Electric Co Ltd

Inventors

• Kawahara Toshio
• Okamoto Kazumasa
• Matsumoto Kazuhiko
• Utsunomiya Risa
• Matsuba Teruaki
• Matsumoto Hitoshi

Classifications

• H10D62/8303

  Diamond · CPC title

• H10D62/882

  Graphene · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D30/6758

  characterised by the insulating substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title