Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9236306-B2
Application number	US-201214130476-A
Country	US
Kind code	B2
Filing date	Nov 28, 2012
Priority date	Dec 29, 2011
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A method for manufacturing a semiconductor device according to this specification solves the problem in the prior art that the silicon on the edge of an oxide layer in an LDMOS drift region is easily exposed and causes breakdown of an LDMOS device. The method includes: providing a semiconductor substrate comprising an LDMOS region and a CMOS region; forming a sacrificial oxide layer on the semiconductor substrate; removing the sacrificial oxide layer; forming a masking layer on the semiconductor substrate after the sacrificial oxidation treatment; using the masking layer as a mask to form an LDMOS drift region, and forming a drift region oxide layer above the drift region; and removing the masking layer. The method is applicable to a BCD process and the like.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate comprising an LDMOS region and a CMOS region;
forming a sacrificial oxide layer on the semiconductor substrate;
removing the sacrificial oxide layer;
forming a masking layer on the semiconductor substrate after removing the sacrificial oxide layer;
forming an LDMOS drift region using the masking layer as a mask;
forming a drift region oxide layer on the drift region; and
removing the masking layer; and
forming a gate oxide and a gate of the CMOS on the semiconductor substrate after removing the masking layer.

2. The method according to claim 1 , wherein the masking layer has a thickness of 250 to 400 angstroms.

3. The method according to claim 1 , wherein the masking layer comprising a masking silicon nitride layer and a masking oxide layer, the masking silicon nitride layer is positioned above the masking oxide layer.

4. The method according to claim 3 , wherein the masking silicon nitride layer has a thickness of 200 to 350 angstroms; the masking oxide layer has a thickness of 50 to 100 angstroms.

5. The method according to claim 3 , wherein the masking silicon nitride layer is formed by thermal oxide growth at a temperature of 600 to 800 degrees.

6. The method according to claim 3 , wherein the masking oxide layer is formed by thermal oxide growth at a temperature of 800 to 1000 degrees.

7. The method according to claim 1 , wherein a stripping thickness of the sacrificial oxide layer is larger than a forming thickness of the sacrificial oxide layer.

8. The method according to claim 7 , wherein the forming thickness of the sacrificial oxide layer is 200 to 400 angstroms, the stripping thickness of the sacrificial oxide layer is 300 to 600 angstroms.

9. The method according to claim 1 , wherein the drift region oxide layer has a thickness of 500 to 1000 angstroms.

10. The method according to claim 1 , wherein the LDMOS drift region is formed subsequent to forming the masking layer.

11. The method according to claim 1 , wherein the drift region oxide layer is formed directly on the drift region.

Assignees

• Csmc Technologies Fab1 Co Ltd
• Csmc Technologies Fabi Co Ltd

Inventors

• Wu Hsiaochia
• Fang Shilin
• Lo Tsehuang
• Chen Zhengpei
• Zhang Shu
• He Yanqiang

Classifications

• H10D84/856

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title

• H10D84/0179

  the gate conductors having different shapes or dimensions · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/0165

  the components including complementary IGFETs, e.g. CMOS devices · CPC title

• H10D84/0142

  the gate conductors having different shapes or dimensions · CPC title