Method of manufacturing semiconductor device having doped layer

Patent metadata

Field	Value
Publication number	US-9236259-B2
Application number	US-201414276213-A
Country	US
Kind code	B2
Filing date	May 13, 2014
Priority date	May 28, 2013
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A method of manufacturing a semiconductor device having a doped layer may be provided. The method includes providing a substrate having a first region and a second region, forming a gate dielectric layer on the substrate, forming a first gate electrode layer on the gate dielectric layer, forming a first doped layer on the first gate electrode layer, forming a first capping layer on the first doped layer, forming a mask pattern on the first capping layer in the first region, the mask pattern exposing the first capping layer in the second region, removing the first capping layer and the first doped layer in the second region, removing the mask pattern, and forming a second doped layer on the first capping layer in the first region and the first gate electrode layer in the second region.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate having a first region and a second region;
forming a gate dielectric layer on the substrate;
forming a first gate electrode layer on the gate dielectric layer;
forming a first doped layer on the first gate electrode layer;
forming a first capping layer on the first doped layer;
forming a mask pattern on the first capping layer in the first region, the mask pattern exposing the first capping layer in the second region;
removing a portion of the first capping layer and the first doped layer formed in the second region;
forming a second doped layer on the first gate electrode layer in the second region;
forming a second capping layer on the second doped layer;
performing a heat treatment process;
removing the second capping layer, the second doped layer, the first capping layer, and the first doped layer after performing the heat treatment process; and
forming a second gate electrode layer on the first gate electrode layer.

2. The method as claimed in claim 1 , wherein the substrate has a cell array region and a peripheral circuit region; and
the first and second regions are formed in the peripheral circuit region.

3. The method as claimed in claim 1 , wherein
the first doped layer includes a first silicon oxide layer having n-type impurities, and
the second doped layer includes a second silicon oxide layer having p-type impurities.

4. The method as claimed in claim 1 , wherein the first and second doped layers have a thickness of about 3 to about 20 nm, respectively.

5. The method as claimed in claim 1 , wherein at least one of the first and second doped layers is formed by an atomic layer deposition (ALD) process.

6. The method as claimed in claim 5 , wherein the first doped layer is formed by the ALD process, which includes at least five steps, and the at least five steps include,
a first step of injecting a phosphorus source gas into the chamber,
a second step of purging the phosphorus source gas from the chamber,
a third step of injecting an oxygen source gas into the chamber,
a fourth step of purging the oxygen source gas from the chamber, and
a fifth step of injecting a silicon source gas into the chamber.

7. The method as claimed in claim 5 , wherein the second doped layer is formed by the ALD process, which includes at least five steps, and the five steps include,
a first step of injecting a boron source gas into the chamber,
a second step of purging the boron source gas from the chamber,
a third step of injecting an oxygen source gas into the chamber,
a fourth step of purging the oxygen source gas from the chamber, and
a fifth step of injecting a silicon source gas into the chamber.

8. The method as claimed in claim 5 , wherein the ALD process is performed in a temperature range of from about 200 to about 500° C.

9. The method as claimed in claim 1 , wherein at least one of the first and second capping layers include a silicon oxide layer.

10. The method as claimed in claim 1 , wherein the heat treatment process is performed in a temperature range of from about 900 to about 1100° C. and in a time range of from 1 to 30 sec.

11. The method as claimed in claim 1 , wherein the first doped layer has n-type impurities and the second doped layer has p-type impurities, and the n-type impurities are diffused to the first gate electrode layer in the first region and the p-type impurities are diffused to the first gate electrode layer in the second region while performing the heat treatment process.

12. The method as claimed in claim 1 , wherein the removing the second capping layer, the second doped layer, the first capping layer, and the first doped layer is performed by using a chemical solution including hydrofluoric acid.

13. The method as claimed in claim 1 , wherein the first gate electrode layer includes polycrystalline silicon, and the second gate electrode layer includes at least one of tungsten (W) and tungsten silicide (WSix).

14. The method as claimed in claim 1 , wherein the forming a first doped layer forms the first doped layer by an ALD process and the forming a second doped layer forms the second doped layer by a chemical vapor deposition (CVD) process.

15. The method as claimed in claim 14 , wherein the forming a first doped layer includes performing the ALD process at temperatures within a first temperature range, the forming a second doped layer includes performing the CVD process at temperatures within a second temperature range, and a maximum temperature of the second temperature range is higher than a maximum temperature of the first temperature range.

16. The method as claimed in claim 14 , wherein the first doped layer has n-type impurities and the second doped layer has p-type impurities, and the n-type impurities are diffused to the first gate electrode layer in the first region and the p-type impurities are diffused to the first gate electrode layer in the second region while forming the second doped layer by using the CVD process.

17. The method as claimed in claim 14 , further comprising:
removing the second doped layer, the first capping layer, and the first doped layer after forming the second doped layer by using the CVD process; and
forming the second gate electrode layer on the first gate electrode layer.

18. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate having a first region and a second region;
providing an electrode layer on the semiconductor substrate;
providing a capping layer and a first doped layer on the electrode layer;
selectively removing the capping layer and the first doped layer over the second region; and
forming a second doped layer on the first capping layer in the first region and on the electrode layer in the second region;
removing the second doped layer, the capping layer, the first doped layer; and
forming electrode patterns by patterning the electrode layer exposed by the removing.

19. The method as claimed in claim 18 , wherein the first doped layer includes one of n-type and p-type impurities and the second doped layer includes the other of n-type and p-type impurities.

20. The method as claimed in claim 19 , further comprising:
performing a heat treatment after the forming the second doped layer to diffuse impurities to the gate electrode layer.

21. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate having a first region and a second region;
forming a gate dielectric layer on the substrate;
forming a first gate electrode layer on the gate dielectric layer;
forming a first doped layer on the first gate electrode layer;
forming a first capping layer on the first doped layer;
forming a mask pattern on the first capping layer in the first region, the mask pattern exposing the first capping layer in the second region;
removing a portion of the first capping layer and the first doped layer formed in the second region;
forming a second doped layer on the first gate electrode layer in the second region;
forming a second capping layer on the second doped layer; and
performing a heat treatment process against the first and second doped layers,
wherein at least one of the first and second doped layers is formed by an atomic layer deposition (ALD) process.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jo Eun-Young
• Kang Jong-Hoon
• Kim Tae-Gon
• Choi Han-Mei

Classifications

• H10P32/171

  being group IV material · CPC title

• H10P32/141

  the applied layer comprising oxides only · CPC title

• H10D64/01312

  the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition · CPC title

• H10D64/01306 Primary

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10D64/661

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671) · CPC title