Chip-type electric double layer capacitor cell and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9236198-B2
Application number	US-201414264835-A
Country	US
Kind code	B2
Filing date	Apr 29, 2014
Priority date	Nov 5, 2009
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A chip-type electric double layer capacitor includes: a resin case having a housing space provided therein and formed of insulating resin; first and second external terminals inserted into the resin case by insert injection molding, each having a first portion exposed to an outer surface of the resin case for external contact and a second portion exposed to an inner surface of the housing space for internal contact; a sealing portion including a groove portion provided in the resin case along a circumference of at least one of the first and second external terminals and a resin filling the groove portion; and an electric double layer capacitor cell mounted in the housing space and electrically connected to the second portion of the first and second external terminals.

First claim

What is claimed is:

1. A chip-type electric double layer capacitor comprising:
a resin case having a housing space provided therein and formed of insulating resin;
first and second external terminals substantially entirely inserted into the resin case, each of the terminals having a first portion exposed to an outer surface of the resin case for external contact and a second portion exposed to an inner surface of the housing space for internal contact;
a sealing portion including a groove portion provided in the resin case along a circumference of at least one of the first and second external terminals and a resin filling the groove portion; and
an electric double layer capacitor cell mounted in the housing space and electrically connected to the second portion of the first and second external terminals,
wherein the second portion of the first and second external terminals extends to side surfaces connected to a mounting surface for the chip-type electric double layer capacitor.

2. The chip-type electric double layer capacitor of claim 1 , wherein the sealing portion is provided to both the first and second external terminals individually.

3. The chip-type electric double layer capacitor of claim 2 , wherein the sealing portion encloses the circumference of the first and second external terminals.

4. The chip-type electric double layer capacitor of claim 2 , wherein the sealing portion is provided in part of the circumference of the first and second external terminals.

5. The chip-type electric double layer capacitor of claim 4 , wherein the groove portion is provided in the inner surface of the housing space along a circumference of the second portion of the first and second external terminals.

6. The chip-type electric double layer capacitor of claim 4 , wherein the groove portion is provided in the outer surface of the resin case along a circumference of the first portion of the first and second external terminals.

7. The chip-type electric double layer capacitor of claim 1 , wherein the first portion of the first and second external terminals is exposed to the same outer surface of the resin case, and
the same outer surface is provided as the mounting surface for the chip-type electric double layer capacitor.

8. The chip-type electric double layer capacitor of claim 1 , wherein the resin case comprises:
a lower case for providing the housing space of which a top surface is opened and formed together with the first and second external terminals by insert injection molding; and
an upper cap mounted on the lower case so as to cover the housing space.

9. The chip-type electric double layer capacitor of claim 8 , wherein the upper cap is mounted on the lower case by using an adhesive.

10. The chip-type electric double layer capacitor of claim 1 , wherein the electric double layer capacitor cell is electrically connected to the second portion of the first and second external terminals by welding or ultrasonic welding.

11. The chip-type electric double layer capacitor of claim 1 , wherein the first and second external terminals are inserted into the resin case to penetrate the resin case by insert injection molding.

12. The chip-type electric double layer capacitor of claim 1 , wherein the groove portion is provided in an inner or outer surface of a wall of the resin case along the circumference of the at least one of the first and second external terminals, and
the groove portion has a depth, from the inner or outer surface, that extends through less than an entire thickness of the wall.

13. The chip-type electric double layer capacitor of claim 1 , wherein the first and second external terminals are in a wall of the resin case and are substantially entirely located between a plane defined by an outer surface of the wall and a plane defined by an inner surface of the wall.

Assignees

• Samsung Electro Mech

Inventors

• Jung Chang Ryul
• Lee Sung Ho
• Park Dong Sup
• Jung Hyun Chul
• Cho Yeong Su
• Lee Sang Kyun

Classifications

• H01G11/80 Primary

  Gaskets; Sealings · CPC title

• H01G11/74 Primary

  Terminals, e.g. extensions of current collectors · CPC title

• H01G11/84

  Processes for the manufacture of hybrid or EDL capacitors, or components thereof · CPC title

• H01G9/016

  Electricity · mapped topic

• Y10T29/417

  Cross-Sectional Technologies · mapped topic