Circuit for enhancing robustness of sub-threshold SRAM memory cell

US9236115B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9236115-B2
Application numberUS-201214369651-A
CountryUS
Kind codeB2
Filing dateDec 27, 2012
Priority dateDec 28, 2011
Publication dateJan 12, 2016
Grant dateJan 12, 2016

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Abstract

Official abstract text for this publication.

A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.

First claim

Opening claim text (preview).

The invention claimed is: 1. A circuit for improving process robustness of sub-threshold SRAM memory cells, wherein, the circuit serves as an auxiliary circuit for a sub-threshold SRAM memory cell, the output (V bp ) of the circuit is connected to a PMOS transistor of the sub-threshold SRAM memory cell and a substrate of the PMOS transistor in the circuit; the circuit comprises a detection circuit for a threshold voltage of the PMOS transistor and a differential input and single-e…

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What does patent US9236115B2 cover?
A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a different…
Who is the assignee on this patent?
Univ Southeast
What technology area does this patent fall under?
Primary CPC classification G11C11/417. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 12 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).