Method and apparatus for bit-line sensing gates on an sram cell
US-2015364183-A1 · Dec 17, 2015 · US
US9236115B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9236115-B2 |
| Application number | US-201214369651-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 27, 2012 |
| Priority date | Dec 28, 2011 |
| Publication date | Jan 12, 2016 |
| Grant date | Jan 12, 2016 |
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A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.
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The invention claimed is: 1. A circuit for improving process robustness of sub-threshold SRAM memory cells, wherein, the circuit serves as an auxiliary circuit for a sub-threshold SRAM memory cell, the output (V bp ) of the circuit is connected to a PMOS transistor of the sub-threshold SRAM memory cell and a substrate of the PMOS transistor in the circuit; the circuit comprises a detection circuit for a threshold voltage of the PMOS transistor and a differential input and single-e…
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