Implementing dynamic cache enabling and disabling based upon workload

Patent metadata

Field	Value
Publication number	US-9235517-B2
Application number	US-201313964365-A
Country	US
Kind code	B2
Filing date	Aug 12, 2013
Priority date	Aug 12, 2013
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A method, system and memory controller for implementing dynamic enabling and disabling of cache based upon workload in a computer system. Predefined sets of information are monitored while the cache is enabled to identify a change in workload, and selectively disabling the cache responsive to a first identified predefined workload. Monitoring predefined information to identify a second predefined workload while the cache is disabled, and selectively enabling the cache responsive to said identified second predefined workload.

First claim

What is claimed is:

1. A method for implementing dynamic enabling and disabling of cache based upon workload in a computer system comprising:
monitoring predefined sets of information while the cache is enabled to identify a change in workload, and selectively disabling the cache responsive to a first identified predefined workload;
monitoring predefined information to identify a second predefined workload while the cache is disabled, and selectively enabling the cache responsive to said identified second predefined workload, said second predefined workload including an average operation length less than a predefined number of cache lines (CLs) for greater than a predefined time N minutes.

2. The method as recited in claim 1 wherein monitoring predefined sets of information while the cache is enabled includes monitoring predefined locality information, said predefined locality information kept in a cache line for each block of data kept in the cache.

3. The method as recited in claim 1 wherein monitoring predefined sets of information while the cache is enabled includes monitoring predefined cache operation statistics information, said cache operation statistics information including one or more of a number of write hits, a number of overwrites, a total number of writes, and a total number of fast writes.

4. The method as recited in claim 1 wherein monitoring predefined sets of information while the cache is enabled includes monitoring predefined performance metrics information, said predefined performance metrics information including one or more of cache induced bottleneck information, cache utilization information, cache queue depth information, and hardware or software operations response time.

5. The method as recited in claim 1 wherein selectively disabling the cache responsive to a first identified predefined workload includes selectively disabling the cache responsive to an identified predefined substantially sequential write workload.

6. The method as recited in claim 1 wherein selectively disabling the cache responsive to a first identified predefined workload includes selectively disabling the cache responsive to identifying a predefined metric threshold value for at least one of monitored locality information, monitored predefined cache operation statistics information, and monitored predefined performance metrics information.

7. The method as recited in claim 1 wherein monitoring predefined information to identify a second predefined workload while the cache is disabled includes monitoring a running average write operation arrival rate.

8. The method as recited in claim 1 wherein monitoring predefined information to identify a second predefined workload while the cache is disabled includes monitoring an average write operation size.

9. The method as recited in claim 1 wherein selectively enabling the cache responsive to said identified second predefined workload includes selectively enabling the cache responsive to an identified predefined workload being different than a substantially sequential write workload.

10. A computer system comprising:
a memory controller for implementing dynamic enabling and disabling of a cache based upon workload in the computer system,
a processor;
said cache coupled to said memory controller and said processor;
a memory coupled to said memory controller and said processor cache;
said memory controller monitoring predefined sets of information while said cache is enabled to identify a change in workload, and said memory controller selectively disabling said cache responsive to a first identified predefined workload;
said memory controller monitoring predefined information to identify a second predefined workload while said cache is disabled, and said memory controller selectively enabling said cache responsive to said identified second predefined workload, said second predefined workload including an average operation length less than a predefined number of cache lines (CLs) for greater than a predefined time N minutes.

11. The system as recited in claim 10 wherein said memory controller monitoring predefined sets of information while the cache is enabled includes said memory controller monitoring predefined locality information, said predefined locality information kept in a cache line for each block of data kept in said cache.

12. The system as recited in claim 10 wherein said memory controller monitoring predefined sets of information while said cache is enabled includes said memory controller monitoring predefined cache operation statistics information, said cache operation statistics information including one or more of a number of write hits, a number of overwrites, a total number of writes, and a total number of fast writes.

13. The system as recited in claim 10 wherein said memory controller monitoring predefined sets of information while said cache is enabled includes said memory controller monitoring predefined performance metrics information, said predefined performance metrics information including one or more of cache induced bottleneck information, cache utilization information, cache queue depth information, and hardware or software operations response time.

14. The system as recited in claim 10 wherein said memory controller selectively disabling said cache responsive to a first identified predefined workload includes said memory controller selectively disabling said cache responsive to identifying a predefined metric threshold value, initiating cache flushing and saving a caching write operation arrival rate.

15. The system as recited in claim 10 wherein said memory controller selectively disabling said cache responsive to a first identified predefined workload includes said memory controller selectively disabling said cache responsive to an identified predefined substantially sequential write workload.

16. The system as recited in claim 10 wherein said memory controller selectively disabling the cache responsive to a first identified predefined workload includes said memory controller selectively disabling said cache responsive to identifying a predefined metric threshold value for at least one of monitored locality information, monitored predefined cache operation statistics information, and monitored predefined performance metrics information.

17. The system as recited in claim 10 wherein said memory controller monitoring predefined information to identify a second predefined workload while said cache is disabled includes said memory controller monitoring a running average write operation arrival rate.

18. The system as recited in claim 10 wherein said memory controller monitoring predefined information to identify a second predefined workload while the cache is disabled includes said memory controller monitoring an average write operation size.

19. The system as recited in claim 10 wherein said memory controller selectively enabling said cache responsive to said identified second predefined workload includes said memory controller selectively enabling the cache responsive to an identified predefined workload being different than a substantially sequential write workload.

20. The system as recited in claim 10 wherein said memory controller selectively enabling said cache responsive to said identified second predefined workload includes said memory controller identifying a predefined threshold value for at least one of an average write operation size, and a running average write operation arrival rate.

Assignees

• Globalfoundries Inc

Inventors

• Anderson Clark A
• Gerhard Adrian C
• Navarro David

Classifications

• G06F12/0866

  for peripheral storage systems, e.g. disk cache · CPC title

• G06F2212/502

  using adaptive policy · CPC title

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F12/0888

  using selective caching, e.g. bypass · CPC title