System and method with reference voltage partitioning for low density parity check decoding

Patent metadata

Field	Value
Publication number	US-9235467-B2
Application number	US-201414165135-A
Country	US
Kind code	B2
Filing date	Jan 27, 2014
Priority date	Mar 15, 2013
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes partitioning circuitry for identifying a set of soft-decision reference voltages having the smallest calculated introduced error value based upon the estimated BER of the nonvolatile memory. The controller further includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value to provide a plurality of soft-decision bits representative of the codeword. The controller further includes an LLR look-up table accessible by the read circuitry to provide LLRs to the LDPC decoder for the subsequent decoding of the codeword.

First claim

What is claimed is:

1. A method of providing log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder in a nonvolatile memory storage module, the method comprising:
identifying an estimated bit-error-rate (BER) for the nonvolatile memory storage module;
identifying a plurality of sets of soft-decision reference voltages, each of the plurality of sets of soft-decision reference voltages comprising a plurality of individual soft-decision reference voltages and each of the individual soft-decision reference voltages in each set of soft-decision reference voltages separated from each other by a distance equal to a selected soft-decision reference voltage partitioning value, wherein the selected soft-decision reference voltage partitioning value is different for each of the plurality of sets of soft-decision reference voltages;
calculating a LLR (log likelihood ratio) introduced error value for each set of soft-decision reference voltages based upon the identified BER of the nonvolatile memory storage module, wherein the calculated LLR introduced error value represents an error introduced by the computation of the LLR for each set of soft-decision reference voltages;
comparing the calculated LLR introduced error value for each set of soft-decision reference voltages to identify the set of soft-decision reference voltages having a smallest calculated LLR introduced error value;
reading an LDPC encoded codeword stored in the nonvolatile memory storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value to provide a plurality of soft-decision bits representative of the codeword;
accessing an LLR look-up table for the nonvolatile memory storage module to extract the LLRs from the LLR look-up table for each of the soft-decision bits; and
providing the extracted LLRs to an LDPC decoder for decoding of the codeword.

2. The method of claim 1 , wherein the nonvolatile memory storage module is a NAND-based flash memory module and further wherein each of the plurality of sets of soft-decision reference voltages comprise an equal number of individual soft-decision reference voltages.

3. The method of claim 1 , wherein the nonvolatile memory storage module is a single-level cell (SLC) memory storage module.

4. The method of claim 1 , wherein the nonvolatile memory storage module is a multi-level cell (MLC) memory storage module.

5. The method of claim 1 , wherein the nonvolatile memory storage module is a triple-level cell (TLC) memory storage module.

6. The method of claim 1 , wherein identifying a plurality of sets of soft-decision reference voltages further comprises:
determining a number of reads of the LDPC encoded codeword to be performed using the soft-decision reference voltages, the number of reads equal to the number of individual soft-decision reference voltages of the sets;
selecting one of the plurality of soft-decision voltage partitioning values; for each of the sets of the plurality of sets; and
partitioning a threshold voltage distribution associated with the BER of the nonvolatile memory storage module based upon the selected soft-decision reference voltage partitioning value and the number of reads to identify the set of soft-decision reference voltages.

7. The method of claim 1 , wherein calculating a LLR (log likelihood ratio) introduced error value for each set of soft-decision reference voltages based upon the identified BER of the nonvolatile memory storage module further comprises calculating a LLR introduced error value using Lloyd's algorithm or Voronoi iteration for each set of soft-decision reference voltages.

8. The method of claim 1 , wherein reading an LDPC encoded codeword stored in the nonvolatile memory storage module further comprises:
identifying at least one hard-decision reference voltage in a threshold voltage distribution associated with the nonvolatile memory storage module;
partitioning the voltage threshold distribution into a plurality of threshold voltage ranges using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value;
applying the set of soft-decision reference voltages to a cell of the nonvolatile memory storage module; and
sensing a voltage level of the cell.

9. A nonvolatile memory controller for providing log likelihood ratios (LLRs) for LDPC decoding, the controller comprising:
partitioning circuitry configured to identify a bit-error-rate (BER) for the nonvolatile memory storage module, to identify a plurality of sets of soft-decision reference voltages, each of the plurality of sets of soft decision reference voltage comprising a plurality of individual soft-decision reference voltages and of the individual soft-decision reference voltages in each set of soft-decision reference voltages separated from each other by a distance equal to a selected soft-decision reference voltage partitioning value, wherein the selected soft-decision reference voltage partitioning value is different for each of the plurality of sets of soft-decision reference voltages, to calculate a LLR (log likelihood ratio) introduced error value for each set of soft-decision reference voltages based upon the identified BER of the nonvolatile memory storage module, wherein the calculated LLR introduced error value represents an error introduced by the computation of the LLR for each set of soft-decision reference voltages and to compare the calculated LLR introduced error value for each set of soft-decision reference voltages to identify the set of soft-decision reference voltages having a smallest calculated LLR introduced error value; and
read circuitry to read an LDPC encoded codeword stored in a nonvolatile memory Storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value and to identify a plurality of soft-decision bits representative of the codeword.

10. The controller of claim 9 , wherein the nonvolatile memory storage module is a NAND-based flash memory module and further wherein each of the plurality of sets of soft-decision reference voltages comprise an equal number of individual soft-decision reference voltages.

11. The controller of claim 9 , wherein the nonvolatile memory storage module is a single-level cell (SLC) memory storage module.

12. The controller of claim 9 , wherein the nonvolatile memory storage module is a multi-level cell (MLC) memory storage module.

13. The controller of claim 9 , wherein the nonvolatile memory storage module is a triple-level cell (TLC) memory storage module.

14. The controller of claim 9 , wherein the partitioning circuitry further comprises circuitry to determine a number reads of the LDPC encoded codeword to be performed using the soft-decision reference voltages, wherein the number of reads is equal to the number of individual soft-decision reference voltages of the sets, to select one of the plurality of soft-decision voltage partitioning values for each of the sets of the plurality of sets and to partition a threshold voltage distribution associated with the BER of the nonvolatile memory storage module based upon the selected voltage partitioning value and the number of reads to identify the set of soft-decision reference voltages.

15. The controller of claim 9 , wherein the partitioning circuitry is configured to calculate the LLR introduced error value using Lloyd's algorithm or Voronoi iteration for each set of soft-decision reference voltages.

16. The controller of claim 9 , wherein the read circuitry for reading an LDPC encoded codeword stor

Assignees

• Pmc Sierra Us Inc

Inventors

• Micheloni Rino
• Marelli Alessia
• Onufryk Peter Z

Classifications

• H03M13/3723

  using means or methods for the initialisation of the decoder · CPC title

• H03M13/1111

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title