Active matrix substrate and display panel including the same

Patent metadata

Field	Value
Publication number	US-9235092-B2
Application number	US-201314377601-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Mar 21, 2012
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

In a region extending along a terminal region located near a substrate end and included in a frame region defined around a rectangular display region, a peripheral circuit section is provided between the display region and a mount region defined in part of the terminal region. The peripheral circuit section includes unit circuit sections that are monolithically provided and are aligned along one side of the display region. The arrangement pitch of outer ones of the unit circuit sections is larger than that of inner ones of the unit circuit sections.

First claim

The invention claimed is:

1. An active matrix substrate comprising:
a rectangular display region in which an image is to be displayed;
a frame region defined around the display region;
a terminal region included in the frame region, defined along one side of the display region, and located near an end of the substrate;
a mount region included in the terminal region and defined along the side of the display region;
a plurality of signal lines located in the display region and extending in parallel with one another in a direction perpendicular to the side of the display region;
a peripheral circuit section located in a portion of the frame region between the display region and the mount region and including a plurality of unit circuit sections that are monolithically provided and are aligned along the side of the display region;
a plurality of first lines located in a portion of the frame region between the display region and the peripheral circuit section and having an outline that narrows from the signal lines toward the unit circuit sections; and
a plurality of second lines located in a portion of the frame region between the peripheral circuit section and the mount region and having an outline that narrows from the unit circuit sections toward the mount region, wherein
an arrangement pitch of outer ones of the unit circuit sections is larger than that of inner ones of the unit circuit sections.

2. The active matrix substrate of claim 1 , further comprising:
a demultiplexer circuit section located in a portion of the frame region between the display region and the peripheral circuit section and including a plurality of first unit circuits that are monolithically provided for each predetermined number of adjacent ones of the signal lines and are aligned along the side of the display region, wherein
the first unit circuits are connected to the predetermined number of adjacent ones of the signal lines,
the unit circuit sections are a plurality of second unit circuits individually connected to the first unit circuits through the first lines,
the first lines are a plurality of first video signal lines that are arranged in a portion of the frame region between the demultiplexer circuit section and the peripheral circuit section such that an outline of the first video signal lines narrows from the first unit circuits toward the second unit circuits, and
the second lines are a plurality of second video signal lines.

3. The active matrix substrate of claim 1 , wherein
the signal lines are a plurality of source signal lines.

4. The active matrix substrate of claim 2 , wherein
each of the second unit circuits includes at least one of an inspection circuit for inputting an inspection signal to an associated one of the first unit circuits or a protection circuit for protecting at least an associated one of the first unit circuits.

5. The active matrix substrate of claim 2 , wherein
a length of the peripheral circuit section along the side of the display region is smaller than a length of the demultiplexer circuit section along the side of the display region.

6. A display panel comprising:
the active matrix substrate of claims 1 ;
a counter substrate facing the active matrix substrate; and
a display medium layer located between the active matrix substrate and the counter substrate.

7. The display panel of claim 6 , wherein
the display medium layer is a liquid crystal layer.

8. An active matrix substrate comprising:
a rectangular display region in which an image is to be displayed;
a frame region defined around the display region;
a terminal region included in the frame region, defined along one side of the display region, and located near an end of the substrate;
amount region included in the terminal region and defined along the side of the display region;
a plurality of signal lines located in the display region and extending in parallel with one another in a direction perpendicular to the side of the display region;
a first peripheral circuit section located in a portion of the frame region between the display region and the mount region and including a plurality of first unit circuit sections that are monolithically provided and are aligned along the side of the display region;
a second peripheral circuit section located in a portion of the frame region between the first peripheral circuit section and the mount region and including a plurality of second unit circuit sections that are monolithically provided, are individually connected to the first unit circuit sections, and are aligned along the side of the display region;
a plurality of first lines located in a portion of the frame region between the display region and the first peripheral circuit section and having an outline that narrows from the signal lines toward the first unit circuit sections;
a plurality of second lines located in a portion of the frame region between the first peripheral circuit section and the second peripheral circuit section and having an outline that narrows from the first unit circuit sections toward the second unit circuit sections; and
a plurality of third lines located in a portion of the frame region between the second peripheral circuit section and the mount region and having an outline that narrows from the second unit circuit sections toward the mount region, wherein
an arrangement pitch of outer ones of the first unit circuit sections is larger than that of inner ones of the first unit circuit sections, and/or an arrangement pitch of outer ones of the second unit circuit sections is larger than that of inner ones of the second unit circuit sections.

9. The active matrix substrate of claim 8 , further comprising:
a demultiplexer circuit section located in a portion of the frame region between the display region and the first peripheral circuit section and including a plurality of first unit circuits that are monolithically provided for each predetermined number of adjacent ones of the signal lines and are aligned along the side of the display region, wherein
the first unit circuits are connected to the predetermined number of adjacent ones of the signal lines,
the first unit circuit sections are a plurality of second unit circuits individually connected to the first unit circuits through the first lines,
the second unit circuit sections are a plurality of third unit circuits individually connected to the second unit circuits through the second lines,
the first lines are a plurality of first video signal lines that are arranged in a portion of the frame region between the demultiplexer circuit section and the first peripheral circuit section such that an outline of the first video signal lines narrows from the first unit circuits toward the second unit circuits,
the second lines are a plurality of second video signal lines that are arranged in a portion of the frame region between the first peripheral circuit section and the second peripheral circuit section such that an outline of the second video signal lines narrows from the second unit circuits toward the third unit circuits, and
the third lines are a plurality of third video signal lines.

10. The active matrix substrate of claim 8 , wherein
the signal lines are a plurality of source signal lines.

11. The active matrix substrate of claim 9 , wherein
each of the second unit circuits is an inspection circuit for inputting an inspection signal to an associated one of the first unit circuits, and
each of the third unit circuits is a protection circuit for protecting at least an associated one of the first unit circuits.

12. The active matrix substrate of claim 9 , wherein
each of the se

Assignees

• Sharp Kk

Inventors

• Yamaguchi Takahiro
• Furuta Shige
• Yokoyama Makoto
• Nishi Shuji
• Fujikawa Yohsuke

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G09G3/3688

  suitable for active matrices only · CPC title

• G02F2001/13456

  Physics · mapped topic

• H01L27/124

  Electricity · mapped topic