Influence clock data recovery settling point by applying decision feedback equalization to a crossing sample

Patent metadata

Field	Value
Publication number	US-9231802-B2
Application number	US-201213727442-A
Country	US
Kind code	B2
Filing date	Dec 26, 2012
Priority date	Dec 26, 2012
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.

First claim

What is claimed is:

1. An apparatus comprising:
a first module coupled to an input signal and operable to generate an edge signal using a first clock signal, wherein said first module further comprises:
a first path coupled to said input signal, said first path comprising:
a first preamplifier;
a first summing node coupled to said first preamplifier; and
a first latch coupled to said first summing node and said first clock signal;

a second path coupled to said input signal, said second path comprises:
a second preamplifier;
a summing node coupled to said second preamplifier and operable to apply feedback to its input signal based on a previously generated data sample; and
a second latch coupled to said second summing node; and

a multiplexer coupled to said first latch and said second latch, said multiplexer operable to select an output between said first latch and said second latch based on an exclusive OR of a first and a second previously generated data samples; and

a second module operable to receive said edge signal and further operable to generate a data sampling phase signal, wherein said edge signal influences a settling point of said data sampling phase signal.

2. The apparatus of claim 1 further comprising:
a third module operable to generate a data sample signal using a second clock signal; and
a fourth module operable to generate an error sample signal using a third clock signal and wherein said first module is a decision feedback equalizer.

3. The apparatus of claim 1 wherein said second module comprises:
a phase detector operable to receive said edge sample signal and generate a plurality of delta phases therefrom;
a loop filter coupled to said phase detector operable to average said plurality of delta phases and generate a phase code; and
a phase interpolator coupled to said loop filter operable to generate said data sampling phase based upon said phase code.

4. The apparatus of claim 3 wherein said plurality of delta phases are generated as a function of said edge sample signal, a current data sample, and a prior data sample.

5. The apparatus of claim 1 further comprising a plurality of said first modules, wherein each of said plurality of modules operates on its own set of clocks.

6. The apparatus of claim 1 further comprising a linear equalizer configured to shape an input pulse response.

7. A receiver for arriving at a clock and data recovery settling point of a data sampling point signal, said apparatus comprising:
a first module coupled to receive an input signal and operable to employ decision feedback equalization (DFE) on the input signal and operable to generate an edge sample signal therefrom using a first clock signal, wherein said first module further comprises:
a first branch coupled to said input signal, said first path comprising:
a first preamplifier;
a first summing node coupled to said first preamplifier; and
a first latch coupled to said first summing node and said first clock signal;

a second branch coupled to said input signal, said second path comprises:
a second preamplifier;
a summing node coupled to said second preamplifier and operable to apply feedback to its input signal based on a previously generated data sample; and
a second latch coupled to said second summing node; and

a multiplexer coupled to said first latch and said second latch, said multiplexer operable to select an output between said first latch and said second latch based on an exclusive OR of a first and a second previously generated data samples; and

a timing recovery module coupled to said first module and operable to receive said edge sample signal and generate a data sampling phase signal based on said edge sample signal.

8. The receiver of claim 7 wherein said first module comprises:
wherein said first branch is operable to apply DFE to said input signal to generate said edge sample signal using said first clock signal, wherein said edge sample signal influences a settling point of said data sampling signal;
wherein said second branch is operable to generate an error sample signal using a second clock signal; and
a third branch comprising said multiplexer operable to generate a data sample signal using a third clock signal.

9. The receiver of claim 7 wherein said timing recovery module comprises:
a phase detector operable to receive said edge sample signal and generate a plurality of delta phases therefrom;
a loop filter coupled to said phase detector operable to average said plurality of delta phases and generate a phase code; and
a phase interpolator coupled to said loop filter operable to generate said phase code based upon values contained within a lookup table and further operable to generate said data sampling phase signal.

10. The receiver of claim 7 wherein said first module further comprises an odd path and an even path simultaneously processing, wherein further said odd path uses a first clock cycle and said even path uses a second clock cycle.

11. An apparatus comprising:
a first module coupled to an input signal and operable to generate an edge signal using a first clock signal; wherein said first module further comprises:
a first path coupled to said input signal, said first path comprising:
a first preamplifier;
a first summing node coupled to said first preamplifier and operable to apply a first feedback to its input signal based on a previously generated data sample; and
a first latch coupled to said first summing node;

a second path coupled to said input signal, said second path comprising:
a second preamplifier;
a second summing node coupled to said second preamplifier and operable to apply a second feedback to its input signal based on a previously generated data sample; and
a second latch coupled to said second summing node; and

a multiplexer coupled to said first latch and said second latch, said multiplexer operable to select an output between said first latch and said second latch based on an exclusive OR of a first and a second previously generated data samples; and

a second module operable to receive said edge signal and further operable to generate a data sampling phase signal, wherein said edge signal influences a settling point of said data sampling phase signal.

12. The apparatus of claim 11 further comprising:
a third module operable to generate a data sample signal using a second clock signal; and
a fourth module operable to generate an error sample signal using a third clock signal and wherein said first module is a decision feedback equalizer.

13. The apparatus of claim 11 , wherein said second module comprises:
a phase detector operable to receive said edge sample signal and generate a plurality of delta phases therefrom;
a loop filter coupled to said phase detector operable to average said plurality of delta phases and generate a phase code; and
a phase interpolator coupled to said loop filter operable to generate said data sampling phase based upon said phase code.

14. The apparatus of claim 13 , wherein said plurality of delta phases are generated as a function of said edge sample signal, a current data sample, and a prior data sample.

15. The apparatus of claim 14 , further comprising a plurality of said first modules, wherein each of said plurality of modules operates on its own set of clocks.

16. The apparatus of claim 14 , further comprising a linear equalizer configured to shape an input pulse response.

17. An apparatus comprising:
a first module coupled to an input signal and operable to generate an edge signal using a first clock

Assignees

• Nvidia Corp

Inventors

• Zhong Lizhi
• Balan Vishnu
• Amin Arif Al
• Maheshwari Sanjeev

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/03248

  Arrangements for operating in conjunction with other apparatus · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L27/01 Primary

  Equalisers {(baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005)} · CPC title

• H04L7/0332

  with an integrator-detector · CPC title