Methods and apparatus for frequency offset estimation and correction prior to preamble detection of direct sequence spread spectrum (DSSS) signals

Patent metadata

Field	Value
Publication number	US-9231648-B2
Application number	US-201514638299-A
Country	US
Kind code	B2
Filing date	Mar 4, 2015
Priority date	May 21, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Methods and apparatus for frequency offset estimation and correction prior to preamble detection of DSSS signals. An integrated circuit is disclosed including a receiver circuit having an input coupled to receive a DSSS signal, the receiver circuit configured to sample the DSSS signal and to output a sequence of digital samples; carrier frequency offset estimation logic configured to perform a carrier frequency offset estimation on the digital samples; carrier frequency correction logic configured to correct the carrier frequency of the sequence of digital samples using the carrier frequency offset estimation and to output a sequence of corrected digital samples; offset quadrature phase shift keying (O-QPSK) demodulation logic configured to perform demodulation on the corrected digital samples and further configured to output symbols corresponding to the corrected digital samples; and preamble identification configured to identify and detect a preamble sequence in the symbols. Additional methods and apparatus are disclosed.

First claim

What is claimed is:

1. An integrated circuit for receiving direct sequence spread spectrum (DSSS) signals, comprising:
a receiver circuit having an input coupled to receive a DSSS signal from an over the air interface and configured to down convert the received signal form a carrier frequency to a frequency selected from one of a baseband frequency and an intermediate frequency, the receiver circuit including analog to digital converter circuitry coupled to the input and configured to sample the DSSS signal, and further configured to output a sequence of digital samples corresponding to the DSSS signal;
carrier frequency offset estimation logic coupled to the sequence of digital samples from the receiver circuit and configured to perform a carrier frequency offset estimation on the sequence of digital samples;
carrier frequency correction logic coupled to the carrier frequency offset estimation logic and configured to correct the carrier frequency of the sequence of digital samples using the carrier frequency offset estimation, and configured to output a sequence of corrected digital samples;
offset quadrature phase shift keying (O-QPSK) demodulation logic coupled to the carrier frequency correction logic and configured to perform demodulation on the corrected digital samples and further configured to output symbols corresponding to the corrected digital samples; and
preamble identification logic coupled to receive the symbols output by the O-QPSK demodulation logic and configured to identify and detect a preamble sequence in the symbols.

2. The integrated circuit of claim 1 , and further including a microprocessor coupled to a memory storing instructions for the microprocessor which, when executed by the microprocessor, cause the microprocessor to perform at least the carrier frequency estimation logic and the carrier frequency correction logic.

3. The integrated circuit of claim 2 , the carrier frequency offset estimation logic configured to perform a carrier frequency offset estimation on the sequence of digital samples further including:
multiply logic configured to calculate, for each of a number of L samples, where L is an integer number of preamble bits, a product of a complex conjugate of each one of the L samples and the next sample in the sequence of digital samples;
summing logic coupled to receive the products and configured to form a sum of the products, d; and
multiplier logic configured to determine a carrier offset frequency by multiplying a sample frequency fs by 1/(2 times π) times the quantity of an angle operator applied to the quantity d.

4. The integrated circuit of claim 3 , the carrier frequency correction logic configured to use the carrier frequency offset estimation to correct the carrier frequency further including:
multiply logic configured to multiply each digital sample n with n ranging from zero to L−1 by the quantity e−j2π(Δf/fs)n, where Δf is a carrier frequency offset, and further configured to output the resulting products to form a corrected digital sample for each digital sample.

5. The integrated circuit of claim 2 , the preamble identification logic further including:
logic configured to receive the symbols output by the O-QPSK demodulation logic and configured to calculate differential chip values;
logic configured to accumulate the differential chip values for L words, where L is an integer number of preamble bits;
logic configured to perform a correlation between a predetermined chip sequence corresponding to a preamble and the accumulated differential chip values; and
logic configured to compare the correlation to a threshold.

6. The integrated circuit of claim 5 , and further including:
logic configured to output a preamble detected signal, responsive to the compare.

7. A method for performing preamble detection in a direct sequence spread spectrum (DSSS) signaling system, comprising:
receiving DSSS signals on an over the air interface;
sampling the received DSSS signals using a sampling frequency fs;
converting the samples of the received DSSS signals to form digital samples in a sequence representative of the DSSS signals;
using the digital samples, performing a carrier frequency offset estimation to determine a carrier frequency offset Δf;
using the carrier frequency offset Δf, correcting the digital samples to form corrected digital samples representative of the DSSS signal with a corrected carrier frequency;
subsequently, performing offset quadrature phase shift keying (O-QPSK) demodulation for the corrected digital samples to form demodulated corrected digital samples; and
using one or more predetermined preamble sequences, correlating known preamble values to a differential sequence formed from the demodulated corrected digital samples in order to detect a preamble sequence present in the received DSSS signals.

8. The method of claim 7 , and performing the carrier frequency offset further including:
for each of a number of L samples, where L is an integer corresponding to a number of preamble bits, forming a product of the complex conjugate of each one of the digital samples and the next digital sample in the sequence of digital samples;
calculating a total sum of the products, d; and
using an angle operator, forming the carrier frequency offset Δf by multiplying the sampling frequency fs by 1/(2 times π) multiplied by the quantity given from the angle operator applied to the quantity d.

9. The method of claim 8 , and forming corrected digital samples further including:
for each digital sample, forming a corrected digital sample using an index n ranging from zero to L−1 samples, the quantity formed by multiplying each digital sample value from zero to L−1 by the quantity e−j2π(Δf/fs)n.

10. The method of claim 8 , and forming corrected digital samples further including:
for each corrected digital sample, forming a buffer length of integer L2 which is less than L; and
for each corrected digital sample, using an index n ranging from zero to L2−1 digital samples, multiplying each digital sample value for n from zero to L2−1 by the quantity e−j2π(Δf/fs)n.

11. The method of claim 10 , and further including forming the integer L2 by dividing the integer L by k, where k is an integer from one to four.

12. The method of claim 8 , in which L is a positive integer in a range from 64 to 1536.

13. The method of claim 7 , in which the sampling frequency fs is an oversampled frequency of at least twice a chip rate.

14. A communications device for receiving direct sequence spread spectrum (DSSS) signals, comprising:
a receiver coupled to an input and configured to receive a DSSS signal and to down convert the DSSS signal to an intermediate frequency;
the receiver including analog to digital converter circuitry coupled to sample the received DSSS signal and configured to output a sequence of digital samples corresponding to the DSSS signal;
carrier frequency offset estimation logic coupled to receive the digital samples and configured to perform a carrier frequency offset estimation on the sequence of digital samples;
carrier frequency correction logic configured to use the carrier frequency offset estimation to correct the carrier frequency and outputting a sequence of corrected digital samples;
offset quadrature phase shift keying (O-QPSK) demodulation logic coupled to receive the corrected digital samples and configured to perform demodulation on the corrected digital samples and to output symbols corresponding to the corrected digital samples; and
preamble identification logic coupled to the O-QPSK demodulation logic and configured to identify and detect a

Assignees

• Texas Instruments Inc

Inventors

• Lingam Srinivas
• Schmidl Timothy Mark

Classifications

• H04B1/7075 Primary

  with code phase acquisition · CPC title

• H04B1/7087 Primary

  Carrier synchronisation aspects · CPC title

• H04L25/02

  Details {; arrangements for supplying electrical power along data transmission lines (systems for transmitting signals via power distribution lines H04B3/54)} · CPC title

• H04L23/00

  Apparatus or local circuits for systems other than those covered by groups H04L15/00 - H04L21/00 · CPC title