Chip package with isolated pin, isolated pad or isolated chip carrier and method of making the same

Patent metadata

Field	Value
Publication number	US-9231118-B2
Application number	US-201313797724-A
Country	US
Kind code	B2
Filing date	Mar 12, 2013
Priority date	Mar 12, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A chip package with isolated pin, isolated pad or isolated chip carrier and a method of making the same are disclosed. In one embodiment a chip package includes a chip, a package encapsulating the chip, pads or pins disposed on a first side of the package and an isolation pad or an isolation pin disposed on a second side of the package, the isolation pin or the isolation pad electrically isolated from the chip, wherein the chip comprises a magnetic field sensor configured to measure a magnetic field generated outside of the package.

First claim

What is claimed is:

1. A chip package comprising:
a chip;
a package encapsulating the chip;
pads or pins disposed on a first side of the package; and
an isolation pad or an isolation pin disposed on a second side of the package, the isolation pin or the isolation pad electrically isolated from the chip, wherein the isolation pad or the isolation pin is configured to be structurally affixed to an anchor pad of a current trace, the current trace at least partially overlapping the package encapsulating the chip and extending at least partially past an edge of the package, wherein the anchor pad of the current trace is either completely electrically isolated from the current trace or electrically isolated from the current trace except at a bridge, and
wherein the chip comprises a magnetic field sensor configured to measure a magnetic field generated outside of the package.

2. The chip package according to claim 1 , wherein the first side is opposite the second side.

3. The chip package according to claim 1 , wherein the first side is adjacent to the second side.

4. The chip package according to claim 1 , further comprising an additional isolation pin or an additional isolation pad electrically isolated from the chip.

5. The chip package according to claim 1 , wherein no other pin or pad, or no other isolation pin or pad is disposed on the second side.

6. The chip package according to claim 1 , wherein no other pin or pad is disposed on the second side.

7. The chip package according to claim 1 , further comprising a chip carrier, the chip disposed on the chip carrier.

8. The chip package according to claim 7 , further comprising an isolation layer, the isolation layer disposed between the chip and the chip carrier, wherein the isolation layer comprises a larger area than the chip.

9. The chip package according to claim 7 , further comprising a platelet, the platelet disposed between the chip carrier and the chip.

10. The chip package according to claim 9 , wherein a bottom side of the chip carrier is exposed and not covered by a package material of the package.

11. The chip package according to claim 1 , wherein the isolation pin or the isolation pad is electrically isolated from the chip to withstand a breakdown voltage of at least 300 V.

12. A system comprising:
a packaged chip including
a chip;
a package encapsulating the chip;
pins or pads disposed on a first side of the package; and
an isolation pin or an isolation pad disposed on a second side of the package, the isolation pin or the isolation pad electrically isolated from the chip, wherein the chip comprises a magnetic field sensor configured to measure a magnetic field generated outside of the package; and

a component carrier comprising a current trace,
wherein the isolation pin or the isolation pad is attached to the current trace of the component carrier, wherein the pins or the pads are attached to component carrier pads disposed in a distance from the current trace, wherein the current trace comprises an anchor pad, the anchor pad being either completely electrically isolated from the current trace or electrically isolated from the current trace except at a bridge, and wherein the isolation pin or the isolation pad is attached to the anchor pad.

13. The system according to claim 12 , wherein the anchor pad is completely electrically isolated from the current trace.

14. The system according to claim 12 , wherein the anchor pad is electrically isolated from the current trace except at the bridge.

15. The system according to claim 12 , further comprising a chip carrier, wherein the chip carrier is soldered to the current trace, and wherein the chip carrier is isolated from the chip.

16. The system according to claim 12 , wherein the isolation pin or the isolation pad is soldered to the current trace of the component carrier, wherein a package material is disposed between chip carrier and the current trace, and wherein the chip carrier is isolated from the chip.

Assignees

• Infineon Technologies Ag

Inventors

• Ausserlechner Udo

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10F99/00

  Subject matter not provided for in other groups of this subclass · CPC title