Multi-composition gate dielectric field effect transistors

Patent metadata

Field	Value
Publication number	US-9231072-B2
Application number	US-201414179121-A
Country	US
Kind code	B2
Filing date	Feb 12, 2014
Priority date	Feb 12, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming a first material stack and a second material stack on a semiconductor substrate, said first material stack including at least a planar semiconductor oxide-based dielectric portion and a first disposable material portion, and said second material stack including at least a second disposable material portion;
forming a planarization dielectric layer around said first and second material stacks;
replacing said second material stack with a stack including a chemical oxide layer and a U-shaped high-k dielectric portion;
removing said first disposable material portion; and
forming a first gate electrode over said planar semiconductor oxide-based dielectric portion and a second gate electrode within a volume laterally bounded by said U-shaped high-k dielectric portion by deposition and planarization of a work function material layer and a conductive material layer.

2. The method of claim 1 , wherein said first material stack comprises a planar high dielectric constant (high-k) dielectric material portion contacting said planar semiconductor oxide-based dielectric portion and underlying said first disposable material portion.

3. The method of claim 2 , wherein said first material stack further comprises a planar metallic material portion contacting said planar high-k dielectric material portion and said first disposable material portion.

4. The method of claim 1 , wherein said second material stack further includes another planar oxide-based dielectric portion that contacts a bottom surface of said second disposable material portion.

5. The method of claim 1 , further comprising masking said first material stack with a patterned mask layer formed over said first material stack and said planarization dielectric layer while removing said second material stack.

6. The method of claim 1 , further comprising:
forming a contiguous high-k dielectric layer on said chemical oxide layer, a top surface of said planarization dielectric layer, and a top surface of said first disposable material portion; and
removing portions of said contiguous high-k dielectric layer from above a top surface of said planarization dielectric layer, wherein a remaining portion of said contiguous high-k dielectric layer is said U-shaped high-k dielectric portion.

7. The method of claim 1 , further comprising:
forming a stack of a contiguous metallic material layer and a fill material layer in a cavity formed by removal of said second material stack; and
removing portions of said contiguous metallic material layer and said fill material layer from above said top surface of said planarization dielectric layer.

8. The method of claim 7 , further comprising removing a remaining portion of said fill material layer simultaneously with removal of said first disposable material portion.

9. The method of claim 1 , wherein said first gate electrode comprises a first U-shaped work function material portion and a first conductive material portion, and said second gate electrode comprises a second U-shaped work function material portion and a second conductive material portion, wherein said first and second U-shaped work function material portions have a same composition and a same thickness.

10. The method of claim 9 , wherein said first material stack further comprises a planar metallic material portion contacting said planar high-k dielectric material portion, and said method further comprises forming a U-shaped metallic material portion on said U-shaped high-k dielectric portion, wherein said first U-shape work function material portion is formed on said planar metallic material portion, and said second U-shaped work function material portion is formed on said U-shaped metallic material portion.

Assignees

• IBM

Inventors

• Alptekin Emre
• Kwon Unoh
• Lai Wing L
• Li Zhengwen
• Narayanan Vijay
• Ramachandran Ravikumar
• Vega Reinaldo A

Classifications

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D30/0227

  having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title