Redistribution layers for microfeature workpieces, and associated systems and methods

Patent metadata

Field	Value
Publication number	US-9230859-B2
Application number	US-201113236372-A
Country	US
Kind code	B2
Filing date	Sep 19, 2011
Priority date	Aug 30, 2006
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.

First claim

I claim:

1. A microfeature workpiece system, comprising;
a first microfeature workpiece having a semiconductor substrate with a first surface, a second surface opposite the first surface, and a redistribution layer over the semiconductor substrate, wherein the semiconductor substrate includes no operable microfeature devices formed between the first and second surfaces and wherein the semiconductor substrate comprises silicon;
a second microfeature workpiece adjacent the first microfeature workpiece, the second microfeature workpiece having at least one operable microfeature device and an interconnect structure electrically coupled to the microfeature device; and
a conductive via extending entirely through the semiconductor substrate of the first microfeature workpiece, wherein the conductive via electrically connects the interconnect structure to the redistribution layer of the first microfeature workpiece.

2. The system of claim 1 wherein the interconnect structure extends through the second microfeature workpiece.

3. The system of claim 1 wherein the redistribution layer is positioned proximate to the first surface of the semiconductor substrate.

4. The system of claim 1 wherein the second microfeature workpiece includes a wafer having a plurality of unsingulated dies.

5. The system of claim 1 , further comprising an adhesive attached between facing surfaces of the first and second microfeature workpieces.

6. The system of claim 1 , further comprising one or more of a memory, a processor and an input/output device, and wherein the first and second microfeature workpieces are included in at least one of the memory, the processor and the input/output device.

7. A microfeature workpiece system, comprising:
a first microfeature workpiece including—
a silicon substrate having a first surface, a second surface facing opposite from the first surface, and no integrated circuit between the first and second surfaces of the silicon substrate,
a conductive structure that includes a lateral line and a bond site proximate to the first surface, and
a first conductive via connected to the lateral line and extending entirely through the silicon substrate; and

a second microfeature workpiece having a first surface, a second surface facing opposite from the first surface and toward the second surface of the silicon substrate, at least one operable microfeature device, and a second conductive via connected to the first conductive via of the first microfeature workpiece.

8. The system of claim 7 wherein the first conductive via extends to the second surface of the first microfeature workpiece, and wherein the second conductive via extends to the second surface of the second microfeature workpiece.

9. The system of claim 7 wherein the first conductive via includes a conductive lining and a fill material having a composition different than that of the conductive lining, and wherein the via extends along a generally straight axis generally transverse to the first surface of the first microfeature workpiece.

10. The system of claim 7 wherein the second microfeature workpiece includes a memory device.

11. The system of claim 7 wherein the second microfeature device includes an imaging device.

12. The system of claim 7 , wherein at least one of the first and second interconnect structures includes a conductive cap connected to the other of the first and second interconnect structures.

13. The system of claim 1 , further comprising an adhesive attached between facing surfaces of the first and second microfeature workpieces, wherein the interconnect structure extends at least partially through the adhesive.

14. The system of claim 1 , further comprising:
a conductive cap electrically connecting the first and second interconnect structures; and
an adhesive between the first and second microfeature workpieces and surrounding the conductive cap.

15. The system of claim 7 wherein the first conductive via extends beyond the second surface of the first microfeature workpiece and toward the second conductive via.

16. The system of claim 7 , further comprising:
a conductive cap electrically connecting the first and second vias; and
an adhesive between the corresponding second surfaces of the first and second microfeature workpieces and surrounding the conductive cap.

17. The system of claim 1 , wherein:
the conductive via is a first conductive via,
the interconnect structure of the second microfeature workpiece includes a second conductive via electrically coupled to the microfeature device;
the first and second conductive vias are laterally aligned.

18. The system of claim 1 , wherein the no operable microfeature devices include no operable integrated circuit.

19. A microfeature workpiece system, comprising:
a silicon die having a first surface, a redistribution layer at the first surface, a second surface facing opposite from the first surface, a first conductive via extending entirely through the silicon die and electrically connected to the redistribution layer, and no operable microfeature devices between the first and second surfaces of the silicon die; and
a microfeature workpiece having a first surface, a second surface facing opposite from the first surface of the microfeature workpiece, at least one operable microfeature device positioned between the first and second surfaces of the microfeature workpiece, and a second conductive via extending entirely through the microfeature workpiece and electrically connected to the first conductive via and the microfeature device, the second surfaces of the silicon die and the microfeature workpiece facing toward each other, the redistribution layer of the silicon die facing opposite from the first surface of the microfeature workpiece.

20. The system of claim 19 wherein the first and second conductive vias are laterally aligned.

Assignees

• Pratt David
• Micron Technology Inc

Inventors

• Pratt David

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/9226

  with via interconnections · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title