Apparatuses and methods for mapping memory addresses to redundant memory

Patent metadata

Field	Value
Publication number	US-9230692-B2
Application number	US-201313919850-A
Country	US
Kind code	B2
Filing date	Jun 17, 2013
Priority date	Jun 17, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Apparatuses and methods related to redundant memory and mapping memory addresses to redundant memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of redundant memory sections. A programmable element block includes a plurality of programmable element sets. A programmable element set is configured to be programmed with location information for a redundant memory section of the plurality of redundant memory sections and further programmed with a respective memory address to be mapped to a redundant memory element of the redundant memory section located by the location information. A programmable element block logic is configured to associate a memory address programmed in a programmable element set with a redundant memory element of the redundant memory section located by the respective location information programmed in the programmable element set.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of memory sections;
a plurality of redundant memory sections, wherein a redundant memory section of the plurality of redundant memory sections is associated with a respective memory section of the plurality of memory sections;
a redundant memory programmable element block including a plurality of programmable element sets, wherein a programmable element set of the plurality of programmable element sets is configured to be programmed with a respective memory address to be mapped to a redundant memory element of a redundant memory section of the plurality of redundant memory sections, and further programmed with location information for the redundant memory section that includes the redundant memory element to which the respective memory address is to be mapped, and wherein the programmable element set of the plurality of programmable element sets is configured to be further programmed with enable information indicating that the programmable element set has been programmed; and
programmable element block logic coupled to the redundant memory programmable block and configured to associate a memory address programmed in a programmable element set of the plurality of programmable element sets with a redundant memory element of the redundant memory section located by the respective location information programmed in the programmable element set.

2. The apparatus of claim 1 wherein the redundant memory section of the plurality of redundant memory sections further includes a redundant address latch for the redundant memory element.

3. The apparatus of claim 1 wherein the programmable element sets comprise antifuse sets.

4. The apparatus of claim 1 wherein the programmable element block logic is configured to associate the memory address with a next available redundant memory element of the redundant memory section.

5. The apparatus of claim 1 wherein the plurality of memory sections are included in a memory block.

6. The apparatus of claim 1 wherein the redundant memory section of the plurality of redundant memory sections that is associated with the respective memory section of the plurality of memory sections is limited to having memory addresses of the respective memory section of the plurality of memory sections mapped thereto.

7. The apparatus of claim 1 , further comprising redundant memory logic configured to compare incoming memory addresses of memory to be accessed to memory addresses programmed in the redundant memory programmable element block to identify a memory address to be mapped to redundant memory.

8. The apparatus of claim 2 wherein the programmable element block logic is configured to latch the memory address in the redundant memory address latch of the redundant memory element to associate a memory address programmed in a programmable element set.

9. An apparatus, comprising
a redundant memory section including a redundant memory element;
a plurality of programmable element sets, each of the programmable element sets of the plurality of programmable element sets including programmable elements configured to be programmed with a memory address to be mapped and programmed with respective location information for a redundant memory section, and wherein the programmable element set of the plurality of programmable element set is configured to be further programmed with cable information;
a redundant memory element configured to have a memory address mapped thereto, wherein the redundant memory element is included in a redundant memory section located by the location information programmed in any of the plurality of programmable element sets; and
a redundant address latch associated with the redundant memory element and configured to latch the memory address programmed in the programmable element set of the plurality of programmable elements sets that includes the location information locating the redundant memory section including the redundant memory element.

10. The apparatus of claim 9 wherein the redundant memory element comprises a column of redundant memory.

11. The apparatus of claim 9 wherein the redundant memory element comprises a row of redundant memory.

12. The apparatus of claim 9 , further comprising a memory section wherein the memory section includes the memory address latched in the redundant address latch.

13. The apparatus of claim 9 wherein the redundant memory element is a first memory element included in a first redundant memory section and the redundant address latch is a first redundant address latch, and the apparatus further comprises:
a second redundant memory element configured to have a memory address mapped thereto, wherein the second redundant memory element is included in a second redundant memory section located by the location information programmed in any of the plurality of programmable element sets; and
a second redundant address latch associated with the second redundant memory element and configured to latch the memory address programmed in the programmable element set of the plurality of programmable element sets that includes the location information locating the second redundant memory section, wherein the second memory section is a different memory section from the first memory section.

14. The apparatus of claim 9 wherein the redundant memory element is a first memory element included in a first redundant memory section and the redundant address latch is a first redundant address latch, and the apparatus further comprises:
a second redundant memory element configured to have a memory address mapped thereto, wherein the second redundant memory element is included in the first redundant memory section located by the location information programmed in a second one of the plurality of programmable element sets; and
a second redundant address latch associated with the second redundant memory element and configured to latch the memory address programmed in the second one of the plurality of programmable element sets.

15. A method comprising:
decoding location information for redundant memory, the redundant memory including redundant memory elements;
checking availability of a first redundant memory element included in the redundant memory;
associating a memory address with the first redundant memory element responsive to the first redundant memory element being available by latching the memory address in a redundant address latch associated with the first redundant memory element;
checking availability of a second redundant memory element included in the redundant memory responsive to the first redundant memory element not being available;
associating the memory address with the second redundant memory element responsive to the second redundant memory element being available; and
checking availability of a third redundant memory element included in the redundant memory responsive to the second redundant memory element not being available.

16. A method comprising:
decoding location information for redundant memory, the redundant memory including redundant memory elements;
checking availability of a first redundant memory element included in the redundant memory;
associating a memory address with the first redundant memory element responsive to the first redundant memory element being available by latching the memory address in a redundant address latch associated with the first redundant memory element; and
checking availability of a second redundant memory element included in the redundant memory responsive to the first redundant memory element not being available;

Assignees

• Micron Technology Inc

Inventors

• Eichmeyer Seth

Classifications

• G11C29/785

  with redundancy programming schemes · CPC title

• G11C29/76 Primary

  using address translation or modifications · CPC title