Apparatus for dual purpose charge pump

Patent metadata

Field	Value
Publication number	US-9230636-B2
Application number	US-201314137808-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Dec 20, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Described is an apparatus which comprises: a first power supply node to provide a first power supply, a second power supply node, and a third power supply node; a first transistor which is operable to couple the first and second power supply nodes; and a charge pump circuit to provide a boosted voltage to the third power supply node in one mode, and to recover charge from the second power node in another mode. Described is a memory unit which comprises: a DRAM which is operable to be refreshed; a gated power supply node coupled to the DRAM to provide a gated power supply to the DRAM; and a charge recycling circuit to recover charge from the gated power supply node after the DRAM is refreshed.

First claim

We claim:

1. An apparatus comprising:
a first power supply node to provide a first power supply, a second power supply node, and a third power supply node;
a first transistor which is operable to couple the first and second power supply nodes;
a charge pump circuit to provide a boosted voltage to the third power supply node in one mode, and to recover charge from the second power node in another mode; and
memory peripheral circuits to receive power from the second power supply node.

2. The apparatus of claim 1 further comprises a second transistor which is operable to couple the third power supply node to the first power supply node.

3. The apparatus of claim 2 further comprises a third transistor which is operable to couple the first power supply node to a fourth power supply node.

4. The apparatus of claim 3 further comprises a memory array coupled to the fourth power supply node.

5. The apparatus of claim 3 further comprises a fourth transistor coupled in parallel to the third transistor, wherein the fourth transistor is operable to couple the fourth power supply node to the first power supply node.

6. The apparatus of claim 5 further comprises a fifth transistor which is operable to provide the boosted voltage to one or more drivers.

7. The apparatus of claim 6 , wherein the one or more drivers include write wordline drivers and read wordline drivers.

8. The apparatus of claim 1 further comprises a voltage regulator to provide the first power supply to the first power supply node.

9. An apparatus comprising:
a DRAM which is operable to be refreshed;
a first power supply node coupled to the DRAM to provide a first power supply to the DRAM;
a transistor coupled between a second power supply node and the first supply node to enable charge recovery from the second supply node; and
a charge recycling circuit to recover charge from the first second power supply node after the DRAM is refreshed and supplying the recovered charge to the first power supply node.

10. The apparatus of claim 9 further comprises a capacitive device coupled to the second power supply node through the transistor.

11. The apparatus of claim 9 further comprises logic to periodically activate the charge recycling circuit.

12. An apparatus comprising:
an STT-MRAM which is operable to be scrubbed;
one or more drivers coupled to the STT-MRAM;
a first power supply node coupled to the one or more drivers to provide a first power supply to the one or more drivers; and
a charge recycling circuit to recover charge from a second power supply node after the STT-MRAM is scrubbed and supplying the recovered charge to the first power supply node.

13. The apparatus of claim 12 further comprises a capacitive device coupled to the second power supply node.

14. The apparatus of claim 12 further comprises logic to periodically activate the charge recycling circuit.

15. A system comprising:
a memory unit;
a processor coupled to the memory unit, the processor having an apparatus which comprises:
a first power supply node to provide a first power supply, a second power supply node, and a third power supply node;
a first transistor which is operable to couple the first and second power supply nodes;
a charge pump circuit to provide a boosted voltage to the third power supply node in one mode, and to recover charge from the second power node in another mode; and
memory peripheral circuits to receive power from the second power supply node; and

a wireless interface for allowing the processor to communicate with another device.

16. The system of claim 15 , wherein the memory unit comprises:
an STT-MRAM which is operable to be scrubbed;
one or more drivers coupled to the STT-MRAM;
a power supply node coupled to the one or more drivers to provide a power supply to the one or more drivers; and
a charge recycling circuit to recover charge from a gated power supply node after the STT-MRAM is scrubbed and supplying the recovered charge to the power supply node.

17. The system of claim 16 further comprises a logic unit to periodically activate the charge recycling circuit.

18. The system of claim 15 , wherein the memory unit comprises:
a DRAM which is operable to be refreshed;
a power supply node coupled to the DRAM to provide a power supply to the DRAM;
a transistor coupled between a gated power supply node and the power supply node to enable charge recovery from the gated power supply node; and
a charge recycling circuit to recover charge from the gated power supply node after the DRAM is refreshed and supplying the recovered charge to the power supply node.

19. The system of claim 15 further comprises a voltage regulator to provide the first power supply to the first power supply node.

Assignees

• Meinerzhagen Pascal A
• Kulkarni Jaydeep P
• Khellah Muhammad M
• Dray Cyrille
• Somasekhar Dinesh
• Tschanz James W
• De Vivek K
• Intel Corp

Inventors

• Meinerzhagen Pascal A
• Kulkarni Jaydeep P
• Khellah Muhammad M
• Dray Cyrille
• Somasekhar Dinesh
• Tschanz James W
• De Vivek K

Classifications

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title