Determining a direct memory access data transfer mode

Patent metadata

Field	Value
Publication number	US-9229891-B2
Application number	US-201414153497-A
Country	US
Kind code	B2
Filing date	Jan 13, 2014
Priority date	Nov 15, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

In response to receiving a request for a DMA data transfer, a DMA transfer mode may be determined based on based on the size of the requested DMA data transfer and profile data of an I/O adapter. The profile data for the I/O adapter may include a physical location of the I/O adapter or a number of clients supported by the I/O adapter. The DMA transfer mode may also be determined based on a preference of an application or an I/O device. Moreover, the DMA transfer mode may be determined based on a CPU usage metric being outside of a threshold for the CPU usage metric or on a memory usage metric being outside of a threshold for the memory usage metric.

First claim

What is claimed is:

1. A system for determining a direct memory access (DMA) transfer mode, comprising:
a DMA unit to receive a request for a DMA data transfer and to perform the requested DMA data transfer using a determined DMA transfer mode; and
an I/O adapter to determine the DMA transfer mode for the requested DMA data transfer based on the size of the requested DMA data transfer and profile data of the I/O adapter, the DMA transfer mode being one of a first mode or a second mode,
wherein, in the first mode, a first region of system memory is pre-allocated for use in DMA transfers, and
wherein, in the second mode, a second region of system memory for use in a particular DMA transfer is allocated for the particular DMA transfer and deallocated when the particular DMA transfer is complete.

2. The system of claim 1 , wherein the profile data for the I/O adapter includes a physical location of the I/O adapter.

3. The system of claim 1 , wherein the profile data for the I/O adapter includes a number of clients supported by the I/O adapter.

4. The system of claim 3 ,
wherein the system memory includes a hypervisor and at least one logical partition of the system memory, and
wherein one or more of the clients supported by the I/O adapter is a logical partition.

5. The system of claim 1 , wherein the profile data for the I/O adapter includes an indication as to whether the I/O adapter includes a capability to transfer data using one of two or more network technologies.

6. The system of claim 1 , further comprising the I/O adapter being configured to determine a DMA transfer mode for the requested DMA data transfer based on a preference of an application or an I/O device.

7. The system of claim 1 , further comprising the I/O adapter being configured to determine a DMA transfer mode for the requested DMA data transfer based on a CPU usage metric being outside of a threshold for the CPU usage metric, the CPU usage metric being determined in a time interval immediately previous to the request for a DMA data transfer.

8. The system of claim 1 , further comprising the I/O adapter being configured to determine a DMA transfer mode for the requested DMA data transfer based on a memory usage metric being outside of a threshold for the memory usage metric, the memory usage metric being determined in a time interval immediately previous to the request for a DMA data transfer.

9. The system of claim 5 , wherein the two or more network technologies include Ethernet and Fibre Channel.

Assignees

• IBM

Inventors

• Cardona Omar
• Ochs Matthew R
• Sethi Vikramjit

Classifications

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title