Memory controller, semiconductor memory device and control method thereof

Patent metadata

Field	Value
Publication number	US-9229851-B2
Application number	US-55189809-A
Country	US
Kind code	B2
Filing date	Sep 1, 2009
Priority date	Feb 24, 2009
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.

First claim

What is claimed is:

1. A memory controller configured to control a flash memory including memory cells, the memory controller comprising:
a memory configured to include an access number storing section configured to store a number of read accesses for encoded data stored in a memory cell in association with one of logical addresses provided from a host apparatus; and
a processor configured to include:
an address translator configured to translate the logical addresses to physical addresses of the flash memory;
a storage state checking section configured to, at an interval which is determined by a number of read accesses, check the number of errors in decoding processing of data read from the memory cell; and
a refresh processing section configured to perform refresh processing to restore the encoded data stored in the memory cell, when the number of errors checked by the storage state checking section, is larger than a predetermined number, wherein
the predetermined number of read accesses is set to have a small enough interval with respect to a difference between a number of accesses at which a sign of read disturb occurs and a number of accesses at which error correction is disabled.

2. The memory controller according to claim 1 , wherein:
the refresh processing section performs the refresh processing for each physical block unit having memory cells in a degraded state, the physical block unit being a unit of data erasure composed of a predetermined number of memory cells,
the access number storing section stores a number of the read accesses for each logical block unit, and
the storage state checking section checks the number of errors in the decoding processing for each logical block unit.

3. The memory controller according to claim 1 , wherein:
the refresh processing section performs the refresh processing for each physical block unit having memory cells in a degraded state, the physical block unit being a unit of data erasure composed of a predetermined number of memory cells,
the access number storing section stores a number of the read accesses for each logical block group unit which has a plurality of logical blocks, and
the storage state checking section checks the number of errors in the decoding processing for each logical block group unit.

4. The memory controller according to claim 3 , wherein
the refresh processing section performs the refresh processing when an instruction to perform the refresh processing is given from the host apparatus.

5. The memory controller according to claim 3 , wherein
the storage state checking section checks the storage state of data under a condition in which an error is more likely to occur than a condition of normal data read.

6. The memory controller according to claim 3 , wherein
the storage state checking section checks the storage state of data stored in a memory cell in which an error is likely to occur.

7. The memory controller according to claim 3 , wherein
the refresh processing section performs the refresh processing during an idling time of the host apparatus.

8. A semiconductor memory device configured to store and read encoded data, the semiconductor memory device comprising:
a NAND-type flash memory section having memory cells;
a logical-physical address conversion table configured to perform conversion between a physical address which indicates a position of a memory cell in the NAND-type flash memory section, and a logical address which indicates a position of the memory cell in logical space;
an access number storing section configured to store a number of read accesses to read encoded data from a memory cell in association with the logical address;
a storage state checking section configured to, at an interval which is determined by a number of read accesses, check the number of errors in decoding processing of data read from the memory cell; and
a refresh processing section configured to perform refresh processing to restore the encoded data stored in the memory cell when the number of errors checked by that the storage state checking section is larger than a predetermined number, wherein
the predetermined number of read accesses is set to have a small enough interval with respect to a difference between a number of accesses at which a sign of read disturb occurs and a number of accesses at which error correction is disabled.

9. The semiconductor memory device according to claim 8 , wherein:
the refresh processing section performs the refresh processing for each physical block unit having memory cells in a degraded state, the physical block unit being a unit of data erasure composed of a predetermined number of the memory cells,
the access number storing section stores a number of the read accesses for each logical block unit, and
the storage state checking section checks the number of errors in the decoding processing for each logical block unit.

10. The semiconductor memory device according to claim 8 , wherein:
the refresh processing section performs the refresh processing for each physical block unit having memory cells in a degraded state, the physical block unit being a unit of data erasure composed of a predetermined number of the memory cells,
the access number storing section stores a number of the read accesses for each logical block group unit which has a plurality of logical blocks, and
the storage state checking section checks the number of errors in the decoding processing for the each logical block group unit.

11. The semiconductor memory device according to claim 10 , wherein the refresh processing section performs the refresh processing when an instruction to perform the refresh processing is given from a host apparatus.

12. The semiconductor memory device according to claim 10 , wherein the storage state checking section checks the storage state of data under a condition in which an error is more likely to occur than a condition of normal data read.

13. The semiconductor memory device according to claim 10 , wherein the storage state checking section checks the storage state of data stored in a memory cell in which an error is likely to occur.

14. The semiconductor memory device according to claim 10 , wherein the refresh processing section performs the refresh processing during an idling time of a host apparatus.

15. A control method of a semiconductor memory device configured to store and read encoded data, the control method comprising:
storing a number of read accesses for a memory cell, when encoded data is read from the memory cell;
checking a storage state to check the number of errors in decoding processing of data read from the memory cell at an interval which is determined by a predetermined number of read accesses; and
performing refresh processing to restore the encoded data stored in the memory cell, when the number of errors in decoding is larger than a predetermined number, wherein
the predetermined number of read accesses is set to have a small enough interval with respect to a difference between a number of accesses at which a sign of read disturb occurs and a number of accesses at which error correction is disabled.

16. The control method of the semiconductor memory device according to claim 15 , wherein:
the refresh processing is performed for each physical block unit having memory cells in a degraded state, the physical block unit being a unit of data erasure composed of a predetermined number of the memory cells,
a number of read accesses is stored for each logical block unit, and
the checking is performed for each logical block unit.

Assignees

• Sukegawa Hiroshi
• Tsuji Hidetaka
• Takano Shuji
• Toshiba Kk

Inventors

• Sukegawa Hiroshi
• Tsuji Hidetaka
• Takano Shuji

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title