Memory compatibility system and method

Patent metadata

Field	Value
Publication number	US-9229747-B2
Application number	US-201414149229-A
Country	US
Kind code	B2
Filing date	Jan 7, 2014
Priority date	Aug 31, 2011
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system.

First claim

What is claimed is:

1. A memory system, comprising:
a first connector that is configured to connect to a processing system through a first socket, wherein the first connector and first socket conform to a first Dynamic Random Access Memory (DRAM) interface protocol;
a second socket that is configured to connect to a memory module, wherein the second socket and the memory module conform to a second DRAM interface protocol;
a power regulator that is coupled to the second socket and that is configured to couple to a power source through the first connector; and
a virtualization module that is communicatively coupled to the first connector, the second socket, and the power regulator, wherein the virtualization module is configured to:
virtualize the memory module to present a virtual memory module that conforms to the first DRAM interface protocol to the processing system when the first connector is connected to the first socket;
determine a power requirement of the memory module when the memory module is connected to the second socket and communicate the power requirement to the power regulator such that the power regulator regulates power received from the power source through the first connector when the first connector is connected to the first socket to provide a regulated power to the second socket that conforms to the power requirement;
receive first DRAM interface protocol communications from the processing system that are directed to the virtual memory module;
modify the first DRAM interface protocol communications to produce second DRAM interface protocol communications that are compatible with the memory module; and
provide the second DRAM interface protocol communications to the memory module.

2. The memory system of claim 1 , wherein the virtualization of the memory module to present the virtual memory module to the processing system includes retrieving first initialization data that is associated with the second DRAM interface protocol from the memory module and outputting second initialization data that is associated with the first DRAM interface protocol to the processing system.

3. The memory system of claim 2 , wherein the first initialization data includes serial presence detect (SPD) data.

4. The memory system of claim 2 , wherein the virtualization of the memory module to present the virtual memory module to the processing system further includes passing the first initialization data to a memory buffer.

5. The memory system of claim 4 , wherein the first initialization data allows the memory buffer to initialize the memory module without the assistance of a memory controller.

6. The memory system of claim 1 , wherein the modifying the first DRAM interface protocol communications to produce second DRAM interface protocol communications that are compatible with the memory module include receiving a message from the processing system through the first socket and addressing the message to the memory module.

7. The memory system of claim 1 , wherein the virtualization of the memory module to present the virtual memory module to the processing system includes sending the processing system virtualized memory module information associated with the first DRAM interface protocol.

8. The memory system of claim 1 , wherein the first DRAM interface protocol is a double data rate fourth generation (DDR4) DRAM interface protocol standard and the second DRAM interface protocol is a double data rate third generation (DDR3) DRAM interface protocol standard.

9. An information handling system, comprising:
a processing system;
a first socket that is coupled to the processing system and that conforms to a first DRAM interface protocol;
a memory system that is coupled to the processing system through the first socket, the memory system including:
a first connector that is connected to the processing system through a first socket, wherein the first connector conforms to the first DRAM interface protocol;
a second socket that that conforms to a second DRAM interface protocol that was promulgated earlier in time than the first DRAM interface protocol;
a power regulator that is connected to the second socket and to a power source through the first connector;
a memory module that is connected to the second socket and that conforms to the second DRAM interface protocol; and
a virtualization module that is communicatively coupled to the first connector, the second socket, and the power regulator, wherein the virtualization module is configured to:
virtualize the memory module to present a virtual memory module that conforms to the first DRAM interface protocol to the processing system;
determine a power requirement of the memory module and communicate the power requirement to the power regulator such that the power regulator regulates power that is received from the power source through the first connector to provide a regulated power to the second socket that conforms to the power requirement;
receive first DRAM interface protocol communications from the processing system that are directed to the virtual memory module;
modify the first DRAM interface protocol communications to produce second DRAM interface protocol communications that are compatible with the memory module; and
provide the second DRAM interface protocol communications to the memory module.

10. The IHS of claim 9 , wherein the virtualization of the memory module to present the virtual memory module to the processing system includes retrieving first initialization data that is associated with the second DRAM interface protocol from the memory module and outputting second initialization data that is associated with the first DRAM interface protocol to the processing system.

11. The IHS of claim 10 , wherein the virtualization of the memory module to present the virtual memory module to the processing system further includes passing the first initialization data to a memory buffer, and wherein the first initialization data allows the memory buffer to initialize the memory module without the assistance of a memory controller.

12. The IHS of claim 9 , wherein the modifying the first DRAM interface protocol communications to produce second DRAM interface protocol communications that are compatible with the memory module include receiving a message from the processing system through the first socket and addressing the message to the memory module.

13. The IHS of claim 9 , wherein the first DRAM interface protocol is a double data rate fourth generation (DDR4) DRAM interface protocol standard and the second DRAM interface protocol is a double data rate third generation (DDR3) DRAM interface protocol standard.

14. A method, comprising:
providing a memory system including a first connector that conforms to a first DRAM interface protocol, a second socket that conforms to a second DRAM interface protocol, a power regulator that is coupled to the second socket and to a power source through the first connector, and a virtualization module that is communicatively coupled to the first connector, the second socket, and the power regulator;
communicating, using the virtualization module, with a memory module that conforms to the second DRAM interface protocol when the second socket is connected to the memory module;
communicating, using the virtualization module, with a processing system when the first connector is connected to a first socket that conforms to the first DRAM interface protocol and that is coupled to the processing system;
virtualizing, using the virtualization module, the memory module to present a virtual memory module that conforms to the first DRAM interface

Assignees

• Dell Products Lp

Inventors

• Berke Stuart
• Sauber William

Classifications

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G06F9/44557 Primary

  Code layout in executable memory · CPC title

• G06F11/1016

  Error in accessing a memory location, i.e. addressing error · CPC title

• G06F13/409

  Mechanical coupling (back panels H05K7/1438) · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title