Identifying load-hit-store conflicts

Patent metadata

Field	Value
Publication number	US-9229745-B2
Application number	US-201213611006-A
Country	US
Kind code	B2
Filing date	Sep 12, 2012
Priority date	Sep 12, 2012
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A computing device identifies a load instruction and store instruction pair that causes a load-hit-store conflict. A processor tags a first load instruction that instructs the processor to load a first data set from memory. The processor stores an address at which the first load instruction is located in memory in a special purpose register. The processor determines where the first load instruction has a load-hit-store conflict with a first store instruction. If the processor determines the first load instruction has a load-hit store conflict with the first store instruction, the processor stores an address at which the first data set is located in memory in a second special purpose register, tags the first data set being stored by the first store instruction, stores an address at which the first store instruction is located in memory in a third special purpose register and increases a conflict counter.

First claim

What is claimed is:

1. A computer program product for identification of a load instruction and store instruction pair that causes a load-hit-store conflict, the computer program product comprising:
one or more computer-readable storage devices and program instructions stored on at least one of the one or more computer-readable tangible storage devices, wherein the one or more computer-readable storage devices is not construed to include transitory media, the program instructions comprising:
program instructions to tag a first load instruction that instructs the processor to load a first data set from a memory;
program instructions to store an address at which the first load instruction is located in memory in a first special purpose register;
program instructions to determine whether the first load instruction has a load-hit-store conflict with a first store instruction, wherein the load-hit-store conflict occurs when the first load instruction instructs the processor to load the first data set from memory before the first data set has been stored into memory by the first store instruction;
responsive to determining the first load instruction has a load-hit-store conflict with the first store instruction, program instructions to store an address at which the first data set is located in memory in a second special purpose register, to tag the first data set
being stored by the first store instruction, to store an address at which the first store instruction is located in memory in a third special purpose register, and to increase a conflict counter.

2. The computer program product of claim 1 , wherein the program instructions to increase the conflict counter further comprises generating an interrupt and locking all special purpose registers when the conflict counter surpasses a pre-set threshold value.

3. The computer program product of claim 1 , further comprising:
program instructions to tag a second load instruction that instructs the processor to load a second data set from a memory;
program instructions to store an address at which the second load instruction is located in memory in the first special purpose register;
program instructions to determine whether the second load instruction has a load-hit-store conflict with a second store instruction, wherein the load-hit-store conflict occurs when the second load instruction instructs the processor to load the second data set from memory before the second data set has been stored into memory by the second store instruction;
responsive to determining the second load instruction does not have a load-hit-store conflict with the second store instruction, program instructions to delete the address at which the second load instruction is located in memory from the first special purpose register.

4. A computer system for identification of a load instruction and store instruction pair that causes a load-hit-store conflict, the computer system comprising:
one or more processors, one or more computer-readable memories, one or more computer-readable storage devices, wherein the one or more computer-readable storage devices is not construed to include transitory media, and program instructions stored on at least one of the one or more computer-readable storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, the program instructions comprising:
program instructions to tag a first load instruction that instructs the processor to load a first data set from a memory;
program instructions to store an address at which the first load instruction is located in memory in a first special purpose register;
program instructions to determine whether the first load instruction has a load-hit-store conflict with a first store instruction, wherein the load-hit-store conflict occurs when the first load instruction instructs the processor to load the first data set from memory before the first data set has been stored into memory by the first store instruction;
responsive to determining the first load instruction has a load-hit-store conflict with the first store instruction, program instructions to store an address at which the first data set is located in memory in a second special purpose register, to tag the first data set being stored by the first store instruction, to store an address at which the first store instruction is located in memory in a third special purpose register, and to increase a conflict counter.

5. The computer system of claim 4 , wherein the program instructions to increase the conflict counter further comprises generating an interrupt and locking all special purpose registers when the conflict counter surpasses a pre-set threshold value.

6. The computer system of claim 4 , further comprising:
program instructions to tag a second load instruction that instructs the processor to load a second data set from a memory;
program instructions to store an address at which the second load instruction is located in memory in the first special purpose register;
program instructions to determine whether the second load instruction has a load-hit-store conflict with a second store instruction, wherein the load-hit-store conflict occurs when the second load instruction instructs the processor to load the second data set from memory before the second data set has been stored into memory by the second store instruction;
responsive to determining the second load instruction does not have a load-hit-store conflict with the second store instruction, program instructions to delete the address at which the second load instruction is located in memory from the first special purpose register.

Assignees

• Indukuru Venkat R
• Mericas Alexander E
• Sadasivam Satish K
• Valluri Madhavi G
• IBM

Inventors

• Indukuru Venkat R
• Mericas Alexander E
• Sadasivam Satish K
• Valluri Madhavi G

Classifications

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title

• G06F9/44552 Primary

  Conflict resolution, i.e. enabling coexistence of conflicting executables · CPC title