Serializing wrapping trace buffer via a compare-and-swap instruction

US9229724B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9229724-B2
Application numberUS-201313803702-A
CountryUS
Kind codeB2
Filing dateMar 14, 2013
Priority dateMar 14, 2013
Publication dateJan 5, 2016
Grant dateJan 5, 2016

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Embodiments of the disclosure serializing wrapping of a circularly wrapping trace buffer via a compare-and-swap (CS) instruction by a method including executing a CS loop to advance to a location in the buffer indicated by a next free pointer. The method also includes incrementing a master wrap sequence number each time the next free pointer returns to a top of the buffer and executing another CS loop to increment a wrap number stored in a trace block corresponding to the location indicated by the next free pointer. Based upon determining that the wrap number stored in the trace block is one less than or equal to the master wrap sequence number, the method includes reserving space in a buffer associated with the trace block and storing the wrap number stored in the trace block as an old wrap number and incrementing a use-count of the trace block.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for serializing wrapping of a circularly wrapping trace buffer via a compare-and-swap (CS) instruction, the method comprising: executing, by a processor, a first CS loop to advance to a location in the circularly wrapping trace buffer indicated by a next free pointer, wherein the circularly wrapping trace buffer includes a plurality of trace blocks; incrementing a master wrap sequence number each time the next free pointer returns to a top of the circularly wrapping trace buffer; executing a second CS loop to increment a block wrap number stored in one of the plurality of trace blocks corresponding to the location indicated by the next free pointer, wherein the second CS loop is a nested loop within the first CS loop; based upon determining that the block wrap number stored in the one of the plurality of trace blocks is one less than or equal to the master wrap sequence number, reserving space in a buffer associated with the one of the plurality of trace blocks and storing the block wrap number stored in the one of the plurality of trace blocks as an old wrap number; executing a third CS loop to increment an in-use counter of the one of the plurality of trace blocks; based upon determining that the block wrap number for one of the plurality of the trace blocks is equal to the old wrap number after the reserving, executing a write of a data to the buffer associated with the one of the plurality of trace blocks and decrementing the in-use counter of the one of the plurality of trace blocks when the write is complete. 2. The method of claim 1 , further comprising based upon determining that the block wrap number stored in the one of the plurality of trace blocks is not one less than or equal to the master wrap sequence number, canceling the CS instruction. 3. The method of claim 1 , further comprising based upon determining that the block wrap number for the one of the plurality of trace blocks is not equal to the old wrap number, canceling the CS instruction. 4. The method of claim 1 , wherein the old wrap number is stored in a local storage of an application executing the CS instruction. 5. The method of claim 1 , further comprising determining if the buffer associated with the location indicated by the next free pointer has enough space available for the data to be written. 6. The method of claim 5 , based on determining that the buffer associated with the location indicated by the next free pointer does not has enough space available for the data to be written, updating the next free pointer to a start of a next one of the plurality of trace blocks. 7. A computer system for serializing wrapping of a circularly wrapping trace buffer via a compare-and-swap (CS) instruction comprising: a processor configured to perform a method comprising: executing a first CS loop to advance to a location in the circularly wrapping trace buffer indicated by a next free pointer, wherein the circularly wrapping trace buffer includes a plurality of trace blocks; incrementing a master wrap sequence number each time the next free pointer returns to a top of the circularly wrapping trace buffer; executing a second CS loop to increment a block wrap number stored in one of the plurality of trace blocks corresponding to the location indicated by the next free pointer, wherein the second CS loop is a nested loop within the first CS loop; based upon determining that the wrap number stored in the one of the plurality of trace blocks is one less than or equal to the master wrap sequence number, reserving space in a buffer associated with the one of the plurality of trace blocks and storing the wrap number stored in the one of the plurality of trace blocks as an old wrap number; executing a third CS loop to increment an in-use counter of the one of the plurality of trace blocks; based upon determining that the block wrap number for the one of the plurality of trace blocks is equal to the old wrap number after the reserving, executing a write of a data to the buffer associated with the one of the plurality of trace blocks and decrementing the in-use counter of the one of the plurality of trace blocks when the write is complete. 8. The computer system of claim 7 , further comprising based upon determining that the block wrap number stored in the one of the plurality of trace blocks is not one less than or equal to the master wrap sequence number, canceling the CS instruction. 9. The computer system of claim 7 , further comprising based upon determining that the block wrap number for the one of the plurality of trace blocks is not equal to the old wrap number, canceling the CS instruction. 10. The computer system of claim 7 , wherein the old wrap number is stored in a local storage of an application executing the CS instruction. 11. The computer system of claim 7 , further comprising determining if the buffer associated with the location indicated by the next free pointer has enough space available for the data to be written. 12. The computer system of claim 11 , based on determining that the buffer associated with the location indicated by the next free pointer does not has enough space available for the data to be written, updating the next free pointer to a start of a next trace block. 13. A computer program product for serializing wrapping of a circularly wrapping trace buffer via a compare-and-swap (CS) instruction, the computer program product comprising: a non-transitory computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising: computer readable program code configured for: executing a first CS loop to advance to a location in the circularly wrapping trace buffer indicated by a next free pointer, wherein the circularly wrapping trace buffer includes a plurality of trace blocks; incrementing a master wrap sequence number each time the next free pointer returns to a top of the circularly wrapping trace buffer; executing a second CS loop to increment a block wrap number stored in one of the plurality of trace blocks corresponding to the location indicated by the next free pointer, wherein the second CS loop is a nested loop within the first CS loop; based upon determining that the block wrap number stored in the one of the plurality of trace blocks is one less than or equal to the master wrap sequence number, reserving space in a buffer associated with the one of the plurality of trace blocks and storing the block wrap number stored in the one of the plurality of trace blocks as an old wrap number; executing a third CS loop to increment an in-use counter of the one of the plurality of trace blocks; based upon determining that the block wrap number for the one of the plurality of trace blocks is equal to the old wrap number after the reserving, executing a write of a data to the buffer associated with the one of the plurality of trace blocks and decrementing the in-use counter of the one of the plurality of trace blocks when the write is complete. 14. The computer program product of claim 13 , further comprising based upon determining that the block wrap number stored in the trace block is not one less than or equal to the master wrap sequence number, canceling the CS instruction. 15. The computer program product of claim 13 , further comprising based upon determining that the block wrap number for the one of the plurality of trace blocks is not equal to the old wrap number, canceling the CS instruction. 16. The computer program product of claim 13 , further comprising determining if the buffer associate

Assignees

Inventors

Classifications

  • Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

  • Atomic · CPC title

  • G06F9/3814Primary

    Implementation provisions of instruction buffers, e.g. prefetch buffer; banks · CPC title

  • from multiple instruction streams, e.g. multistreaming · CPC title

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What does patent US9229724B2 cover?
Embodiments of the disclosure serializing wrapping of a circularly wrapping trace buffer via a compare-and-swap (CS) instruction by a method including executing a CS loop to advance to a location in the buffer indicated by a next free pointer. The method also includes incrementing a master wrap sequence number each time the next free pointer returns to a top of the buffer and executing another …
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F9/3814. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).