Low drop-out voltage regulator

US9229464B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9229464-B2
Application numberUS-201313955380-A
CountryUS
Kind codeB2
Filing dateJul 31, 2013
Priority dateJul 31, 2013
Publication dateJan 5, 2016
Grant dateJan 5, 2016

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The voltage regulator comprises a regulation loop ( 2 ), which comprises at least a pass transistor ( 18 ), a source transistor ( 28 ), a sensing transistor ( 22 ) and a retention transistor ( 24 ), and a stability compensation circuit ( 10 ), which comprises a first MOS resistor ( 12 ) and a second MOS resistor ( 14 ) coupled with the first MOS resistor ( 12 ). The gate of the second MOS resistor ( 14 ) is coupled to the gate of the pass transistor ( 18 ).

First claim

Opening claim text (preview).

What is claimed is: 1. A voltage regulator comprising: a regulation loop comprising at least a pass transistor, a source transistor, a sensing transistor and a retention transistor, and a stability compensation circuit comprising a first MOS resistor and a second MOS resistor, coupled with the first MOS resistor, wherein a gate of the second MOS resistor is coupled to a gate of the pass transistor, wherein the stability compensation circuit comprises a second node coupled with a drain of the retention transistor and with a drain of the source transistor, and wherein the first MOS resistor and the second MOS resistor are arranged in parallel with drains of the first and second MOS resistors connected to the second node. 2. The voltage regulator according to claim 1 , wherein the stability compensation circuit comprises a first node coupled with a source of the source transistor and with a source of the pass transistor. 3. The voltage regulator according to claim 1 , wherein the stability compensation circuit comprises at least one capacitor coupled by a first terminal with a drain of at least one of the first MOS resistor and the second MOS resistor, and wherein a second terminal of the capacitor is connected to the second node coupled with the drain of the retention transistor and with the drain of the source transistor. 4. The voltage regulator according to claim 1 , wherein the second node is coupled to the gate of the second MOS resistor and to the gate of the pass transistor. 5. The voltage regulator according to claim 2 , wherein the first MOS resistor and the second MOS resistor are arranged in parallel with sources of the first and second MOS resistors connected to the first node. 6. The voltage regulator according to claim 1 , wherein the stability compensation circuit comprises a third resistor between the drains of the first and second MOS resistors and the second node. 7. The voltage regulator according to claim 1 , wherein the pass transistor, the source transistor and the sensing transistor are PMOS transistors. 8. The voltage regulator according to claim 1 , wherein the retention transistor is an NMOS transistor. 9. An electronic device comprising at least one voltage regulator according to claim 1 .

Assignees

Inventors

Classifications

  • G05F1/56Primary

    using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

  • G05F1/595Primary

    semiconductor devices connected in series · CPC title

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Frequently asked questions

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What does patent US9229464B2 cover?
The voltage regulator comprises a regulation loop ( 2 ), which comprises at least a pass transistor ( 18 ), a source transistor ( 28 ), a sensing transistor ( 22 ) and a retention transistor ( 24 ), and a stability compensation circuit ( 10 ), which comprises a first MOS resistor ( 12 ) and a second MOS resistor ( 14 ) coupled with the first MOS resistor ( 12 ). The gate of the second MOS resis…
Who is the assignee on this patent?
Em Microelectronic Marin Sa
What technology area does this patent fall under?
Primary CPC classification G05F1/56. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).