Butt-coupled buried waveguide photodetector

Patent metadata

Field	Value
Publication number	US-9229164-B2
Application number	US-201313868477-A
Country	US
Kind code	B2
Filing date	Apr 23, 2013
Priority date	Apr 23, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A method of forming an integrated photonic semiconductor structure having a photodetector and a CMOS device may include forming the CMOS device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (STI) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolates the first and second silicon-on-insulator region. Within the STI region, a germanium material is deposited adjacent an end facet of the semiconductor optical waveguide. The germanium material forms an active region that receives propagating optical signals from the end facet of the semiconductor optical waveguide.

First claim

What is claimed is:

1. A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device comprising:
forming a well region for the CMOS device;
forming an isolation region extending from a top surface of the photodetector device to an underlying oxide layer for electrically isolating the photodetector device from the well region, wherein the isolation region is in direct physical contact with the underlying oxide layer;
forming a semiconductor optical waveguide for propagating optical signals; and
depositing, within the isolation region, germanium material adjacent to an end facet of the semiconductor optical waveguide,
wherein the deposited germanium material forms an active region of the photodetector device for receiving the propagating optical signals from the end facet of the semiconductor optical waveguide structure.

2. The method of claim 1 , further comprising:
performing a thermal anneal process for simultaneously initiating activating well dopants
within the well region and crystallizing the deposited germanium material that forms the active region.

3. The method of claim 2 , wherein the thermal anneal process comprises heating the integrated photonic semiconductor structure to a temperature of about 1030° C. for a period of about 5 seconds.

4. The method of claim of claim 1 , further comprising:
depositing an insulating oxide fill material over opposing side walls of the semiconductor optical waveguide, wherein the semiconductor optical waveguide comprises a core region and the insulating oxide fill material deposited over the opposing side walls comprises a cladding.

5. The method of claim 4 , wherein the insulating oxide fill material comprises a silicon dioxide (SiO 2 ) material.

6. The method of claim 1 , wherein the deposited germanium material comprises a thickness of about 50-200 nm.

7. The method of claim 1 , wherein the depositing of the germanium material adjacent the end facet comprises utilizing one of a physical vapor deposition (PVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a rapid thermal chemical vapor deposition (RTCVD) process, and a reduced pressure chemical vapor deposition (RPCVD) process.

8. The method of claim 1 , wherein the isolation region comprises a shallow trench isolation (STI) region.

9. The method of claim 1 , wherein the semiconductor optical waveguide is formed from a silicon-on-insulator (SOI) layer located over a buried oxide (BOX) layer.

10. The method of claim 1 , wherein the CMOS device comprises an PET.

11. The method of claim 1 , wherein the semiconductor optical waveguide propagates optical signals having a wavelength of about 1550 nm.

12. The method of claim 1 , wherein the semiconductor optical waveguide propagates optical signals having a wavelength of about 1310 nm.

13. A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device comprising:
forming a well region for the CMOS device;
forming an isolation region for electrically isolating the photodetector device from the well region;
forming a semiconductor optical waveguide for propagating optical signals;
depositing, within the isolation region, germanium material adjacent to an end facet of the semiconductor optical waveguide, wherein the deposited germanium material forms an active region of the photodetector device for receiving the propagating optical signals from the end facet of the semiconductor optical waveguide structure; and
depositing an oxide liner within the isolation region prior to the depositing of the germanium material, wherein the oxide liner separates the end facet of the semiconductor optical waveguide from the adjacent deposited germanium material.

14. The method of claim 13 , wherein the oxide liner comprises a thickness of about 20-40 nm.

15. A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device comprising:
forming a silicon optical waveguide on a second silicon-on-insulator region;
forming a shallow trench isolation region surrounding the silicon optical waveguide, the shallow trench isolation region electrically isolating the first and the second silicon-on-insulator region; and
depositing, within a region of the shallow trench isolation region, germanium material adjacent an end facet of the semiconductor optical waveguide;
wherein the deposited germanium material forms an active region of the photodetector device for receiving propagating optical signals from the end facet of the semiconductor optical waveguide.

16. The method of claim 15 , wherein the deposited germanium material is separated from the end facet of the semiconductor optical waveguide by an oxide liner.

17. The method of claim 16 , wherein the oxide liner comprises an oxide layer having a thickness of about 20-40 nm.

18. The method of claim 15 , wherein the shallow trench isolation region comprises a silicon dioxide (SiO 2 ) fill material.

19. The method of claim 15 , wherein the deposited germanium material comprises a thickness of about 50-200 nm.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Assefa Solomon
• Green William M
• Shank Steven M
• Vlasov Yurii A

Classifications

• G02B6/132

  by deposition of thin films · CPC title

• G02B6/13 Primary

  Integrated optical circuits characterised by the manufacturing method · CPC title

• G02B6/12004 Primary

  Combinations of two or more optical elements · CPC title