Minimum-spacing circuit design and layout for PICA

Patent metadata

Field	Value
Publication number	US-9229044-B2
Application number	US-201213463166-A
Country	US
Kind code	B2
Filing date	May 3, 2012
Priority date	Apr 20, 2012
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

PICA test methods are shown that includes forming semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size; forming logic circuits to control the semiconductor devices; activating the one or more semiconductor devices by providing an input signal; and suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits.

First claim

What is claimed is:

1. A method for testing the resolution of an imaging device, comprising:
forming a plurality of semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size;
forming logic circuits to control the semiconductor devices;
activating the semiconductor devices by providing an input signal; and
suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits.

2. The method of claim 1 , further comprising:
changing the select signals to the logic circuits to suppress light emissions from different semiconductor devices; and
determining whether an imaging device can discriminate between light emission patterns generated under the differing select signals.

3. The method of claim 2 , wherein said determining comprises exposing a picosecond imaging circuit analysis device to light emissions from the semiconductor devices.

4. The method of claim 1 , further comprising connecting outputs of pairs of semiconductor devices to a second logic circuit configured to reproduce the input signal.

5. The method of claim 4 , wherein the output of each second logic circuit is connected as the input signal to a subsequent pair of semiconductor devices.

6. The method of claim 4 , wherein the second logic circuits include a NOR gate that accepts the outputs of the semiconductor devices and a NOT gate which inverts the output of the NOR gate.

7. The method of claim 1 , wherein the logic circuits include two NOR gates, each of which accepts the input signal and a respective select signal.

8. The method of claim 1 , wherein the logic circuits are connected to a drain region of the respective semiconductor devices, such that a low-bias provided by the logic circuit suppresses light emissions from a selected semiconductor device.

9. The method of claim 1 , wherein the semiconductor devices are field effect transistors (FFTs).

10. The method of claim 9 , wherein the input signal is applied to a gate terminal of the FETs to activate the FETs.

11. The method of claim 1 , wherein the distinct shapes are parallel linear arrangements.

12. The method of claim 1 , wherein the target resolution size is based on a minimum feature size of a fabrication technology.

13. A method for testing the resolution of an imaging device, comprising:
forming a plurality of field effect transistors (FETs) having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by distance governed by a minimum feature size of a fabrication technology;
forming two NOR gates, each of which accepts the input signal and a respective select signal, to control the FETs;
activating the FETs by providing an input signal;
suppressing light emissions from one or more of the activated FETs by providing one or more select signals to the NOR gates; and
changing the select signals to the NOR gates to suppress light emissions from different FETs devices.

14. The method of claim 13 , further comprising determining whether an imaging device can discriminate between light emission patterns generated under the differing select signals.

15. The method of claim 14 , wherein said determining comprises exposing a picosecond imaging circuit analysis device to light emissions from the semiconductor devices.

16. The method of claim 13 , wherein the NOR gates are connected to a drain region of the respective FETs, such that a low-bias provided by a NOR gate suppresses light emissions from a selected FET.

17. The method of claim 13 , wherein the input signal is applied to a gate terminal of the FETs.

18. The method of claim 13 , wherein the distinct shapes are parallel linear arrangements.

19. A method for testing the resolution of an imaging device, comprising:
forming a plurality of pairs of semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by distance governed by a target resolution size;
forming first logic circuits configured to control pairs of the semiconductor devices;
forming second logic circuits configured to accept outputs of the respective pairs of semiconductor devices and to reproduce the input signal, wherein the output of each second logic circuit is connected as the input signal to a subsequent pair of semiconductor devices;
activating the semiconductor devices by providing an input signal; and
suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits.

20. The method of claim 19 , wherein the first logic circuits include two NOR gates, each of which accepts the input signal and a respective select signal.

21. The method of claim 19 , wherein the second logic circuits include a NOR gate that accepts the outputs of the semiconductor devices and a NOT gate which inverts the output of the NOR gate.

Assignees

• Ainspan Herschel A
• Kim Seongwon
• Stellari Franco
• Weger Alan J
• IBM

Inventors

• Ainspan Herschel A
• Kim Seongwon
• Stellari Franco
• Weger Alan J

Classifications

• H03K19/094

  using field-effect transistors · CPC title

• H03K19/14 Primary

  using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled (optical logic elements G02F3/00) · CPC title

• G01R31/26 Primary

  Testing of individual semiconductor devices (testing of photovoltaic devices H02S50/10; testing or measuring during manufacture or treatment {H10P74/00}) · CPC title

• G01J2001/4238

  Pulsed light · CPC title

• G01J1/44

  Electric circuits {(for command of an exposure part G03B7/02)} · CPC title