Methods, devices and processes for multi-state phase change devices

Patent metadata

Field	Value
Publication number	US-9227378-B2
Application number	US-201213568509-A
Country	US
Kind code	B2
Filing date	Aug 7, 2012
Priority date	Aug 7, 2012
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Devices include multiple phase change materials connected in parallel between electrodes. Memory cells with multiple parallel phase change materials can be programmed to transition among more than two states representing multiple bits of information. Methods for manufacture and use are also disclosed.

First claim

We claim:

1. A phase change device comprising at least two different phase change materials connected in parallel between electrodes, wherein the at least two different phase change materials comprise a first phase change material and a second phase change material, wherein a crystalline state resistance of the second phase change material is distinguishably larger than a crystalline state resistance of the first phase change material, and wherein each of the first phase change material and the second phase change material is configured to undergo a phase change that is caused by self-heating.

2. The phase change device of claim 1 , wherein the first and second phase change layers form a part of a self-heating phase change memory cell.

3. The phase change device of claim 1 , wherein the crystalline state resistance of the second phase change material is at least two times larger than the crystalline state resistance of the first phase change material.

4. The phase change device of claim 3 , wherein the crystalline state resistance of the second phase change material is at least four times larger than the crystalline state resistance of the first phase change material.

5. The phase change device of claim 4 , wherein a threshold voltage across the parallel phase change materials for crystallizing the second phase change material is greater than a threshold voltage across the parallel phase change materials for crystallizing the first phase change material.

6. The phase change device of claim 3 , further comprising a thermal insulation layer between the first phase change material and the second phase change material.

7. The phase change device of claim 6 , wherein each of the first and second phase change materials is an L-shaped sidewall spacer, the first and second phase change materials electrically connected in parallel between a common lower electrode and a common upper electrode.

8. The phase change device of claim 3 , wherein each of the first phase change material and the second phase change material comprises a chalcogenide material.

9. The phase change device of claim 8 , wherein each of the first and second phase change materials comprise germanium, selenium and tellurium.

10. The memory device of claim 1 , wherein each of the first and second phase change materials is elongated in a vertical direction such that each has a length in the vertical direction that is greater than a width in a horizontal direction, and is configured such that a current which causes the self-heating flows in the vertical direction.

11. The memory device of claim 10 , wherein each of the first and second phase change materials is configured such that self-heating causes the phase change to occur in vertically central regions of the first and second phase change materials.

12. A memory device comprising an array of phase change memory cells, wherein each of the phase change memory cells includes at least two different phase change materials connected in parallel between electrodes, wherein the at least two different phase change materials comprise a first phase change material and a second phase change material, wherein a crystalline state resistance of the second phase change material is larger than a crystalline state resistance of the first phase change material to permit differentiation among information states of the phase change memory cells, and wherein each of the first phase change material and the second phase change material is configured to undergo a phase change that is caused by self-heating.

13. The memory device of claim 12 , wherein each of the phase change memory cells is configured for the self-heating of the at least two different phase change materials by current flow therethrough to effect the phase change.

14. The memory device of claim 12 , further comprising a control unit configured to address and apply electrical signals to the electrodes of each of the phase change memory cells.

15. The memory device of claim 13 , wherein the control unit is capable of programming and reading at least four states of each of the phase change memory cells.

16. The memory device of claim 15 , wherein two phase change materials are connected in parallel between the electrodes of each of the phase change memory cells, and the control unit is configured program by applying between one and four of four electrical signal levels in order to control transitions among four resistive states.

17. The memory device of claim 16 , wherein each of the phase change memory cells can store 2 bits of information.

18. The memory device of claim 16 , wherein one of the two phase change materials has a resistance at least two times greater than a resistance of the other of the two phase change materials.

19. The memory device of claim 12 , wherein each of the phase change memory cells includes n different phase change materials connected in parallel between the electrodes and is capable of exhibiting 2 n resistive states and storing n bits of information.

Assignees

• Colombo Davide
• Erbetta Davide
• Micron Technology Inc

Inventors

• Colombo Davide
• Erbetta Davide

Classifications

• G11C11/5678 Primary

  using amorphous/crystalline phase transition storage elements · CPC title

• Y10T428/24942

  including components having same physical characteristic in differing degree · CPC title

• G11C2013/0078

  Write using current through the cell · CPC title

• B32B7/02 Primary

  Physical, chemical or physicochemical properties · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title