Multilayer printed wiring board having multilayer core substrate

US9226397B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9226397-B2
Application numberUS-201313936420-A
CountryUS
Kind codeB2
Filing dateJul 8, 2013
Priority dateAug 9, 2002
Publication dateDec 29, 2015
Grant dateDec 29, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34 P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34 P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

First claim

Opening claim text (preview).

What is claimed is: 1. A multilayer printed wiring board, comprising: a multilayer core substrate including two inner conductor layers having a plurality of conductor circuits, the inner conductor layers including an inner power supply layer and an inner earth layer, and two outer conductor layers having a plurality of conductor circuits, the outer conductor layers including an outer power supply layer and an outer earth layer, and stacked outwardly of the inner conductor layers; an interlayer insulating layer stacked over each of the outer conductor layers and filling a portion between the conductor circuits in each of the outer conductor layers; and a plurality of through hole structures formed through the multilayer core substrate, the plurality of through hole structures including a first through hole structure and a second through hole structure, the first through hole structure electrically connecting the inner power supply layer and the outer power supply layer, the second through hole structure electrically connecting the inner earth layer and the outer earth layer, wherein the outer power supply layer and the inner earth layer are formed over one another with an insulation layer formed therebetween, the inner power supply layer and the outer earth layer are formed over one another with an insulation layer formed therebetween, each of the inner conductor layers comprises a metallic foil layer, and each of the outer conductor layers comprises a metallic foil layer and a plated layer and is formed such that the inner conductor layers are thicker than the outer conductor layers, respectively. 2. The multilayer printed wiring board according to claim 1 , wherein the inner conductor layers comprise a signal line formed on the same layer as the inner power supply layer and a signal line formed on the same layer as the inner earth layer. 3. A multilayer printed wiring board according to claim 1 , wherein each of the inner conductor layers of the multilayer core substrate has a thickness of 10 to 250 μm. 4. A multilayer printed wiring board according to claim 2 , wherein each of the inner conductor layers of the multilayer core substrate has a thickness of 10 to 250 μm. 5. The multilayer printed wiring board according to claim 1 , wherein each of the inner conductor layers has a thickness α 1 , each of the outer conductor layers has a thickness α 2 , and α 1 and α 2 satisfy α 2 <α 1 <40α 2 . 6. The multilayer printed wiring board according to claim 2 , wherein each of the inner conductor layers has a thickness α 1 , said thickness of an each of the outer conductor layers has a thickness α 2 , and α 1 and α 2 satisfy α 2 <α 1 <40α 2 . 7. The multilayer printed wiring board according to claim 4 , wherein each of the inner conductor layers has a thickness α 1 , each of the outer conductor layers has a thickness α 2 , and α 1 and α 2 satisfy α 2 <α 1 <40α 2 . 8. The multilayer printed wiring board according to claim 1 , wherein each of the outer conductor layers of the multilayer core substrate has a thickness of 10 to 60 μm. 9. The multilayer printed wiring board according to claim 2 , wherein each of the outer conductor layers of the multilayer core substrate has a thickness of 10 to 60 μm. 10. The multilayer printed wiring board according to claim 1 , wherein the inner conductor layers and the outer conductor layers are formed in an order of the outer power supply layer, the inner earth layer, the inner power supply layer and the outer earth layer from one side to the other side of the multilayer core substrate. 11. The multilayer printed wiring board according to claim 6 , wherein the inner conductor layers and the outer conductor layers are formed in an order of the outer power supply layer, the inner earth layer, the inner power supply layer and the outer earth layer from one side to the other side of the multilayer core substrate. 12. The multilayer printed wiring board according to claim 7 , wherein the inner conductor layers and the outer conductor layers are formed in an order of the outer power supply layer, the inner earth layer, the inner power supply layer and the outer earth layer from one side to the other side of the multilayer core substrate.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • relative to the surface, e.g. recessed, protruding · CPC title

  • Bond pads, in general · CPC title

  • H10W90/701Primary

    characterised by the relative positions of pads or connectors relative to package parts · CPC title

  • comprising multiple insulating layers · CPC title

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Frequently asked questions

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What does patent US9226397B2 cover?
A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34 P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor lay…
Who is the assignee on this patent?
Ibiden Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W90/701. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 29 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).