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Circuit and method for clock data recovery and circuit and method for analyzing equalized signal
US9225504B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9225504-B2 |
| Application number | US-201514606600-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 27, 2015 |
| Priority date | May 9, 2014 |
| Publication date | Dec 29, 2015 |
| Grant date | Dec 29, 2015 |
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Abstract
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A clock data recovery method samples an input signal according to a reference clock to generate a plurality of sampling results. A first and a second sampling clocks are generated according to the reference clock. A phase difference between the two sampling clocks is larger than zero and less than half an UI and each UI corresponds to an input data. Successive UIs of the input signal are sampled according to the first and the second sampling clocks to generate a first and a second sampling results in each UI. The two sampling results are compared to generate a comparison result. An adjusting signal is generated according to the comparison result and the input data. The first and the second sampling clocks are adjusted according to the adjusting signal such that the sampling results of each UI substantially correspond to a peak value at the UI of the input signal.
First claim
Opening claim text (preview).
What is claimed is: 1. A clock data recovery circuit for sampling an input signal according to a reference clock to generate a plurality of sampling results, comprising: a clock generation circuit, for generating a first sampling clock and a second sampling clock according to the reference clock, wherein a phase difference between the first sampling clock and the second sampling clock is larger than 0 and smaller than half a UI (unit interval) of the input signal, and each UI corr…
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Classifications
Electricity · mapped topic
- H04L7/0016Primary
Electricity · mapped topic
- H04L7/007Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9225504B2 cover?
- A clock data recovery method samples an input signal according to a reference clock to generate a plurality of sampling results. A first and a second sampling clocks are generated according to the reference clock. A phase difference between the two sampling clocks is larger than zero and less than half an UI and each UI corresponds to an input data. Successive UIs of the input signal are sample…
- Who is the assignee on this patent?
- Realtek Semiconductor Corp
- What technology area does this patent fall under?
- Primary CPC classification H04L7/0016. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 29 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).