Semiconductor device and logic device
US-2024178228-A1 · May 30, 2024 · US
US9224813B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9224813-B2 |
| Application number | US-201214002344-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 2, 2012 |
| Priority date | Mar 2, 2011 |
| Publication date | Dec 29, 2015 |
| Grant date | Dec 29, 2015 |
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Official abstract text for this publication.
A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a region of the gate stack outside the outer circumference of the ring. The multi-gate cylindrical-shaped nanotube FET operates in volume inversion for ring widths below 15 nanometers. The cylindrical-shaped nanotube FET demonstrates better short channel effect (SCE) mitigation and higher performance (I on /I off ) than conventional transistor devices. The cylindrical-shaped nanotube FET may also be manufactured with higher yields and cheaper costs than conventional transistors.
Opening claim text (preview).
The invention claimed is: 1. An apparatus, comprising: a substrate; a core gate stack on the substrate; a shell gate stack on the substrate, the shell gate stack being disposed around the core gate stack; a ring of semiconductor material disposed between the core gate stack and the shell gate stack, the ring comprising a source region, a drain region, and a channel region, a first ring of insulating material disposed between the ring of semiconductor material and the core…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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