All-tungsten scheme for source/drain contact, source/drain via, and gate via
US-2024395618-A1 · Nov 28, 2024 · US
Three-dimensional (3D) semiconductor device
US9224751B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9224751-B2 |
| Application number | US-201414453403-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 6, 2014 |
| Priority date | Mar 27, 2014 |
| Publication date | Dec 29, 2015 |
| Grant date | Dec 29, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: interlayer dielectrics stacked and spaced apart from each other; a channel layer passing through the interlayer dielectrics; line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics; a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer; a reaction preventing pattern formed on the barrier patte…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
- H10W20/425Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9224751B2 cover?
- A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a r…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W20/425. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 29 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).