Semiconductor device having groove-shaped via-hole

Patent metadata

Field	Value
Publication number	US-9224690-B2
Application number	US-201414310680-A
Country	US
Kind code	B2
Filing date	Jun 20, 2014
Priority date	Jul 31, 2002
Publication date	Dec 29, 2015
Grant date	Dec 29, 2015

Abstract

The semiconductor device has insulating films 40, 42 formed over a substrate 10 ; an interconnection 58 buried in at least a surface side of the insulating films 40, 42 ; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66 a having a pattern bent at a right angle; and buried conductors 70, 72 a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66 a . A groove-shaped via-hole 66 a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66 . Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

First claim

What is claimed is:

1. A semiconductor device comprising:
a rectangular semiconductor substrate including a semiconductor circuit region and four corners;
a first insulating film formed above the rectangular semiconductor substrate;
a second insulating film formed above the first insulating film;
a plurality of guard rings which surround the semiconductor circuit region; and
a first copper layer formed in the first insulating film;
wherein:
one of said guard rings includes a first groove-shaped via formed in the second insulating film;
the first groove-shaped via includes a copper film;
the first groove-shaped via is connected to the first copper layer;
the first groove-shaped via includes a first pattern bent twice each time at an angle of larger than 90 degree at each of the four corners;
the first pattern is bent totally at 90 degree at each of the four corners of the rectangular semiconductor substrate;
another of said guard rings includes a second groove-shaped via formed in the second insulating film
the second groove-shaped via includes a second copper film;
the second groove-shaped via is connected to the second copper layer
the second groove-shaped via includes a second pattern bent twice each time at an angle of larger than 90 degree respectively at each of the four corners; and
the second pattern is bent totally at 90 degree at each of the four corners of the rectangular semiconductor substrate.

2. The semiconductor device according to claim 1 , wherein the first copper layer and the second copper layer include third patterns bent twice each time at an angle of larger than 90 degree at each of the four corners; and
the third patterns is bent totally at 90 degree at each of the four corners of the rectangular semiconductor substrate.

3. The semiconductor device according to claim 1 , further comprising
a first tantalum layer formed in the first insulating film and located between the first copper layer and the first insulating film,
wherein the groove-shaped via includes a second tantalum layer located between the second copper layer and the second insulating film.

4. The semiconductor device according to claim 3 ,
wherein a material of the first insulating film and a material of the second insulating film are substantially same.

5. The semiconductor device of claim 1 , wherein the plurality of guard rings consists of two guard rings.

6. The semiconductor device of claim 1 , wherein the plurality of guard rings consists of three guard rings.

7. The semiconductor device of claim 1 , wherein the plurality of guard rings consists of four guard rings.

8. The semiconductor device according to claim 1 , wherein
the first copper layer surrounds the semiconductor circuit region,
the first copper layer is bent twice each time at an angle of larger than 90° at each of the four corners, and
the first copper layer is bent in total at 90° at each of the four corners of the rectangular semiconductor substrate.

9. The semiconductor device of claim 8 , wherein the first copper layer is bent twice each time at an angle of approximately 135° at each of the four corners.

10. The semiconductor device of claim 8 , wherein the plurality of guard rings consists of two guard rings.

11. The semiconductor device of claim 8 , wherein the plurality of guard rings consists of three guard rings.

12. The semiconductor device of claim 8 , wherein the plurality of guard rings consists of four guard rings.

Assignees

• Fujitsu Semiconductor Ltd
• Socionext Inc

Inventors

• Watanabe Kenichi

Classifications

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/4421

  the principal metal being copper · CPC title