Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9224488-B2
Application number	US-201313830263-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Sep 13, 2012
Publication date	Dec 29, 2015
Grant date	Dec 29, 2015

Abstract

According to one embodiment, a semiconductor memory device includes the following structure. A memory cell array includes memory cells arranged at positions where bit lines and word lines cross are arranged on a semiconductor substrate. A sense amplifier reads data stored in the memory cell. The hookup region includes a transfer transistor arranged between the memory cell array and the sense amplifier. One end of a current path of the transfer transistor is connected to a first interconnect formed between the semiconductor substrate and the bit line. The other end of the current path is connected to the sense amplifier. A guard ring region is arranged between the memory cell array and the hookup region. A contact plug is arranged to overlap the guard ring region.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array in which memory cells arranged at positions where bit lines and word lines cross each other are arranged on a semiconductor substrate;
a sense amplifier configured to read data stored in one of the memory cells via the bit line in a read operation;
a hookup region comprising a transfer transistor arranged between the memory cell array and the sense amplifier, one end of a current path of the t…

Assignees

• Toshiba Kk

Inventors

• Shikata Go
• Futatsuyama Takuya

Classifications

• G11C16/06

  Physics · mapped topic

• G11C16/3418

  Physics · mapped topic

• G11C16/0483 Primary

  Physics · mapped topic

• G11C16/26 Primary

  Physics · mapped topic