P-channel 3D memory array and methods to program and erase the same at bit level and block level utilizing band-to-band and fowler-nordheim tunneling principals

Patent metadata

Field	Value
Publication number	US-9224474-B2
Application number	US-201314019183-A
Country	US
Kind code	B2
Filing date	Sep 5, 2013
Priority date	Jan 9, 2013
Publication date	Dec 29, 2015
Grant date	Dec 29, 2015

Abstract

A p-channel flash memory device including a 3D NAND array has excellent performance characteristics. Techniques for operating 3D, p-channel NAND arrays include selective programming, selective (bit) erase, and block erase. Selective programming bias arrangements induce band-to-band tunneling current hot electron injection to increase threshold voltages in selected cells. Selective erase biasing arrangements induce −FN hole tunneling to decrease threshold voltages in selected cells. Also, block erase bias arrangements induce −FN hole tunneling in selected blocks of cells.

First claim

What is claimed is:

1. A method for operating a 3D, p-channel flash memory, comprising:
programming selected memory cells in the 3D, p-channel flash memory using band-to-band tunneling hot electron injection;
erasing selected blocks of cells using Fowler-Nordheim FN hole tunneling; and
inhibiting erasing in unselected memory cells by local self-boosting.

2. The method of claim 1 , wherein said programming includes applying a positive program voltage to word lines of selected memory cells, and applying negative pass voltages to word lines of unselected memory cells.

3. The method of claim 1 , wherein said programming includes applying a positive program voltage to word lines of selected memory cells, and applying a negative drain side pass voltage to word lines of unselected memory cells on one side (drain side) of the selected memory cell, and a negative source side pass voltage to word lines of unselected memory cells on another side (source side) of the selected memory cell.

4. The method of claim 2 , wherein the positive program voltage has an absolute value magnitude less than 15V.

5. The method of claim 2 , including applying a non-negative voltage to bit lines of unselected memory cells.

6. A method for operating a p-channel, dual gate flash memory, comprising:
erasing selected memory cells in the p-channel, dual gate flash memory using negative Fowler-Nordheim tunneling of holes.

7. A method for inducing hot electron injection in a selected memory cell in a p-channel NAND string in a NAND array, comprising:
applying a program bias arrangement to program a selected memory cell, the program bias arrangement including:
a positive program voltage pulse on a word line coupled with a selected memory cell, blocking flow of carriers between a first semiconductor body region on a first side of the selected memory cell and a second semiconductor body region on a second side of the selected memory cell;
a negative drain side pass voltage pulse on word lines in the plurality of word lines on the first side of the selected memory cell;
a negative source side pass voltage on word lines in the plurality of word lines on the second side of the selected memory cell;
bias voltages to block current flow between a selected bit line and the semiconductor body region on the first side of the selected memory cell during the negative drain side pass voltage pulse thereby causing capacitive boosting of the first semiconductor region to a boosted, negative voltage level, and to allow current flow between a source line and the semiconductor body region on the second side of the selected memory cell thereby coupling the semiconductor body on the second side of the selected memory cell to the source line; and
bias voltages to prevent capacitive boosting in unselected NAND strings during the negative drain side pass voltage pulse.

8. The method of claim 7 , wherein NAND strings in the NAND array include a first switch between a first end of the NAND string and a bit line or reference line and a second switch between a second end of the NAND string and a bit line or reference line, and wherein:
the bias voltages to block current flow between a selected bit line and the semiconductor body region on the first side of the selected memory cell include voltages which turn off the first switch in the NAND string including the selected memory cell; and
the bias voltages to allow current flow between the source line and the semiconductor body region on the second side of the selected cells include voltages which turn on the second switch and apply a reference voltage to the source line.

9. A method for inducing hot electron injection in a selected memory cell in a p-channel NAND string in a NAND array, comprising:
applying a program bias arrangement to program a selected memory cell, the program bias arrangement including:
a positive program voltage pulse on a word line coupled with a selected memory cell, blocking flow of carriers between a first semiconductor body region on a first side of the selected memory cell and a second semiconductor body region on a second side of the selected memory cell;
a negative drain side pass voltage pulse on word lines in the plurality of word lines on the first side of the selected memory cell;
a negative source side pass voltage on word lines in the plurality of word lines on the second side of the selected memory cell; and

bias voltages to block current flow between a selected bit line and the semiconductor body region on the first side of the selected memory cell during the negative drain side pass voltage pulse thereby causing capacitive boosting of the first semiconductor region to a boosted, negative voltage level, and to allow current flow between a source line and the semiconductor body region on the second side of the selected memory cell thereby coupling the semiconductor body on the second side of the selected memory cell to the source line, wherein the NAND array comprises a 3D array.

10. A memory comprising:
a 3D NAND array including a plurality of NAND strings, a NAND string in the array including a plurality of p-channel memory cells arranged in series in an n-type or intrinsic semiconductor body;
a plurality of word lines, word lines in the plurality coupled to corresponding memory cells in the plurality of memory cells; and
control circuitry coupled to the plurality of word lines adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line using a program bias arrangement that induces band-to-band tunneling hot electron injection.

11. The memory of claim 10 , wherein the program bias arrangement includes:
a positive program voltage pulse on a word line coupled with a selected memory cell, blocking flow of carriers between a first semiconductor body region on a first side of the selected memory cell and a second semiconductor body region on a second side of the selected memory cell;
a negative drain side pass voltage pulse on word lines in the plurality of word lines on the first side of the selected memory cell;
a negative source side pass voltage on word lines in the plurality of word lines on the second side of the selected memory cell; and
bias voltages to block current flow between a selected bit line and the semiconductor body region on the first side of the selected memory cell during the negative drain side pass voltage pulse thereby causing capacitive boosting of the first semiconductor region to a boosted, negative voltage level, and to allow current flow between a source line and the semiconductor body region on the second side of the selected memory cell thereby coupling the semiconductor body on the second side of the selected memory cell to the source line.

12. The memory of claim 10 , wherein the control circuitry is adapted for erasing a selected memory cell in the plurality of memory cells using a selective erase bias arrangement.

13. The memory of claim 12 , wherein the selective erase bias arrangement includes:
a negative erase voltage pulse on a word line coupled with a selected memory cell;
a negative drain side voltage pulse on unselected word lines in the plurality of word lines, the negative drain side pass voltage having an absolute magnitude less than the negative erase voltage pulse;
bias voltages to allow current flow between a selected bit line and the NAND string including the selected memory cell during the negative erase voltage pulse, and to allow current flow between a source line and the NAND string including the selected memory cell; and
bias voltages to block current flow between unselected bit lines and NAND strings

Assignees

• Macronix Int Co Ltd

Inventors

• Lue Hang-Ting

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0475 Primary

  comprising two or more independent storage sites which store independent data · CPC title